forked from OSchip/llvm-project
446 lines
11 KiB
LLVM
446 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64B
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBP
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declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
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define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
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; RV64B-LABEL: grev32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: grevw a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: grev32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: grevw a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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define signext i32 @grev32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
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; RV64B-LABEL: grev32_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: add a0, a0, a1
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; RV64B-NEXT: grevw a0, a0, a2
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: grev32_demandedbits:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: add a0, a0, a1
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; RV64ZBP-NEXT: grevw a0, a0, a2
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; RV64ZBP-NEXT: ret
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%d = add i32 %a, %b
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%e = and i32 %c, 31
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%tmp = call i32 @llvm.riscv.grev.i32(i32 %d, i32 %e)
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ret i32 %tmp
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}
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declare i32 @llvm.riscv.grevi.i32(i32 %a)
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define signext i32 @grevi32(i32 signext %a) nounwind {
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; RV64B-LABEL: grevi32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: greviw a0, a0, 13
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: grevi32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: greviw a0, a0, 13
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; RV64ZBP-NEXT: ret
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%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
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ret i32 %tmp
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}
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declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
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define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
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; RV64B-LABEL: gorc32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: gorcw a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: gorc32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: gorcw a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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define signext i32 @gorc32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
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; RV64B-LABEL: gorc32_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: add a0, a0, a1
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; RV64B-NEXT: gorcw a0, a0, a2
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: gorc32_demandedbits:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: add a0, a0, a1
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; RV64ZBP-NEXT: gorcw a0, a0, a2
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; RV64ZBP-NEXT: ret
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%d = add i32 %a, %b
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%e = and i32 %c, 31
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%tmp = call i32 @llvm.riscv.gorc.i32(i32 %d, i32 %e)
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ret i32 %tmp
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}
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define signext i32 @gorci32(i32 signext %a) nounwind {
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; RV64B-LABEL: gorci32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: gorciw a0, a0, 13
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: gorci32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: gorciw a0, a0, 13
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; RV64ZBP-NEXT: ret
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%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
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ret i32 %tmp
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}
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declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
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define signext i32 @shfl32(i32 signext %a, i32 signext %b) nounwind {
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; RV64B-LABEL: shfl32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: shflw a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: shfl32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: shflw a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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define signext i32 @shfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
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; RV64B-LABEL: shfl32_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: add a0, a0, a1
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; RV64B-NEXT: shflw a0, a0, a2
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: shfl32_demandedbits:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: add a0, a0, a1
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; RV64ZBP-NEXT: shflw a0, a0, a2
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; RV64ZBP-NEXT: ret
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%d = add i32 %a, %b
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%e = and i32 %c, 15
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%tmp = call i32 @llvm.riscv.shfl.i32(i32 %d, i32 %e)
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ret i32 %tmp
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}
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define signext i32 @shfli32(i32 signext %a) nounwind {
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; RV64B-LABEL: shfli32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: shfli a0, a0, 13
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: shfli32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: shfli a0, a0, 13
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; RV64ZBP-NEXT: ret
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%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 13)
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ret i32 %tmp
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}
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declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
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define signext i32 @unshfl32(i32 signext %a, i32 signext %b) nounwind {
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; RV64B-LABEL: unshfl32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: unshflw a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: unshfl32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: unshflw a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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define signext i32 @unshfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
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; RV64B-LABEL: unshfl32_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: add a0, a0, a1
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; RV64B-NEXT: unshflw a0, a0, a2
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: unshfl32_demandedbits:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: add a0, a0, a1
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; RV64ZBP-NEXT: unshflw a0, a0, a2
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; RV64ZBP-NEXT: ret
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%d = add i32 %a, %b
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%e = and i32 %c, 15
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%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %d, i32 %e)
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ret i32 %tmp
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}
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define signext i32 @unshfli32(i32 signext %a) nounwind {
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; RV64B-LABEL: unshfli32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: unshfli a0, a0, 13
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: unshfli32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: unshfli a0, a0, 13
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; RV64ZBP-NEXT: ret
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%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 13)
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ret i32 %tmp
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}
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declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
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define i64 @grev64(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: grev64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: grev a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: grev64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: grev a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define i64 @grev64_demandedbits(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: grev64_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: grev a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: grev64_demandedbits:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: grev a0, a0, a1
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; RV64ZBP-NEXT: ret
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%c = and i64 %b, 63
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%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %c)
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ret i64 %tmp
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}
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define i64 @grevi64(i64 %a) nounwind {
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; RV64B-LABEL: grevi64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: grevi a0, a0, 13
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: grevi64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: grevi a0, a0, 13
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 13)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
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define i64 @gorc64(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: gorc64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: gorc a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: gorc64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: gorc a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define i64 @gorc64_demandedbits(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: gorc64_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: gorc a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: gorc64_demandedbits:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: gorc a0, a0, a1
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; RV64ZBP-NEXT: ret
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%c = and i64 %b, 63
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%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %c)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.gorci.i64(i64 %a)
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define i64 @gorci64(i64 %a) nounwind {
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; RV64B-LABEL: gorci64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: gorci a0, a0, 13
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: gorci64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: gorci a0, a0, 13
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 13)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
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define i64 @shfl64(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: shfl64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: shfl a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: shfl64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: shfl a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define i64 @shfl64_demandedbits(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: shfl64_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: shfl a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: shfl64_demandedbits:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: shfl a0, a0, a1
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; RV64ZBP-NEXT: ret
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%c = and i64 %b, 31
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%tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %c)
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ret i64 %tmp
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}
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define i64 @shfli64(i64 %a) nounwind {
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; RV64B-LABEL: shfli64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: shfli a0, a0, 13
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: shfli64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: shfli a0, a0, 13
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 13)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
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define i64 @unshfl64(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: unshfl64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: unshfl a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: unshfl64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: unshfl a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define i64 @unshfl64_demandedbits(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: unshfl64_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: unshfl a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: unshfl64_demandedbits:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: unshfl a0, a0, a1
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; RV64ZBP-NEXT: ret
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%c = and i64 %b, 31
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%tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %c)
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ret i64 %tmp
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}
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define i64 @unshfli64(i64 %a) nounwind {
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; RV64B-LABEL: unshfli64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: unshfli a0, a0, 13
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: unshfli64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: unshfli a0, a0, 13
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 13)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
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define i64 @xpermn64(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: xpermn64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: xperm.n a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: xpermn64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: xperm.n a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b)
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define i64 @xpermb64(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: xpermb64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: xperm.b a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBP-LABEL: xpermb64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: xperm.b a0, a0, a1
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b)
|
|
ret i64 %tmp
|
|
}
|
|
|
|
declare i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b)
|
|
|
|
define i64 @xpermh64(i64 %a, i64 %b) nounwind {
|
|
; RV64B-LABEL: xpermh64:
|
|
; RV64B: # %bb.0:
|
|
; RV64B-NEXT: xperm.h a0, a0, a1
|
|
; RV64B-NEXT: ret
|
|
;
|
|
; RV64ZBP-LABEL: xpermh64:
|
|
; RV64ZBP: # %bb.0:
|
|
; RV64ZBP-NEXT: xperm.h a0, a0, a1
|
|
; RV64ZBP-NEXT: ret
|
|
%tmp = call i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b)
|
|
ret i64 %tmp
|
|
}
|
|
|
|
declare i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b)
|
|
|
|
define i64 @xpermw64(i64 %a, i64 %b) nounwind {
|
|
; RV64B-LABEL: xpermw64:
|
|
; RV64B: # %bb.0:
|
|
; RV64B-NEXT: xperm.w a0, a0, a1
|
|
; RV64B-NEXT: ret
|
|
;
|
|
; RV64ZBP-LABEL: xpermw64:
|
|
; RV64ZBP: # %bb.0:
|
|
; RV64ZBP-NEXT: xperm.w a0, a0, a1
|
|
; RV64ZBP-NEXT: ret
|
|
%tmp = call i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b)
|
|
ret i64 %tmp
|
|
}
|