forked from OSchip/llvm-project
110 lines
3.3 KiB
LLVM
110 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64B
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBE
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declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
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define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind {
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; RV64B-LABEL: bcompress32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: bcompressw a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBE-LABEL: bcompress32:
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; RV64ZBE: # %bb.0:
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; RV64ZBE-NEXT: bcompressw a0, a0, a1
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; RV64ZBE-NEXT: ret
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%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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define signext i32 @bcompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV64B-LABEL: bcompress32_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: add a0, a0, a1
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; RV64B-NEXT: add a1, a2, a3
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; RV64B-NEXT: bcompressw a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBE-LABEL: bcompress32_demandedbits:
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; RV64ZBE: # %bb.0:
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; RV64ZBE-NEXT: add a0, a0, a1
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; RV64ZBE-NEXT: add a1, a2, a3
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; RV64ZBE-NEXT: bcompressw a0, a0, a1
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; RV64ZBE-NEXT: ret
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%e = add i32 %a, %b
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%f = add i32 %c, %d
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%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %e, i32 %f)
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ret i32 %tmp
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}
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declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
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define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind {
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; RV64B-LABEL: bdecompress32:
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; RV64B: # %bb.0:
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; RV64B-NEXT: bdecompressw a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBE-LABEL: bdecompress32:
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; RV64ZBE: # %bb.0:
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; RV64ZBE-NEXT: bdecompressw a0, a0, a1
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; RV64ZBE-NEXT: ret
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%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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define signext i32 @bdecompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV64B-LABEL: bdecompress32_demandedbits:
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; RV64B: # %bb.0:
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; RV64B-NEXT: add a0, a0, a1
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; RV64B-NEXT: add a1, a2, a3
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; RV64B-NEXT: bdecompressw a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBE-LABEL: bdecompress32_demandedbits:
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; RV64ZBE: # %bb.0:
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; RV64ZBE-NEXT: add a0, a0, a1
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; RV64ZBE-NEXT: add a1, a2, a3
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; RV64ZBE-NEXT: bdecompressw a0, a0, a1
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; RV64ZBE-NEXT: ret
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%e = add i32 %a, %b
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%f = add i32 %c, %d
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%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %e, i32 %f)
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ret i32 %tmp
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}
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declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
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define i64 @bcompress64(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: bcompress64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: bcompress a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBE-LABEL: bcompress64:
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; RV64ZBE: # %bb.0:
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; RV64ZBE-NEXT: bcompress a0, a0, a1
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; RV64ZBE-NEXT: ret
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%tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
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define i64 @bdecompress64(i64 %a, i64 %b) nounwind {
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; RV64B-LABEL: bdecompress64:
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; RV64B: # %bb.0:
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; RV64B-NEXT: bdecompress a0, a0, a1
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; RV64B-NEXT: ret
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;
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; RV64ZBE-LABEL: bdecompress64:
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; RV64ZBE: # %bb.0:
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; RV64ZBE-NEXT: bdecompress a0, a0, a1
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; RV64ZBE-NEXT: ret
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%tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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