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llvm-project/llvm/test/CodeGen/RISCV
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Matt Arsenault 4a36e96c3f RegAllocGreedy: Account for reserved registers in num regs heuristic 
This simple heuristic uses the estimated live range length combined
with the number of registers in the class to switch which heuristic to
use. This was taking the raw number of registers in the class, even
though not all of them may be available. AMDGPU heavily relies on
dynamically reserved numbers of registers based on user attributes to
satisfy occupancy constraints, so the raw number is highly misleading.

There are still a few problems here. In the original testcase that
made me notice this, the live range size is incorrect after the
scheduler rearranges instructions, since the instructions don't have
the original InstrDist offsets. Additionally, I think it would be more
appropriate to use the number of disjointly allocatable registers in
the class. For the AMDGPU register tuples, there are a large number of
registers in each tuple class, but only a small fraction can actually
be allocated at the same time since they all overlap with each
other. It seems we do not have a query that corresponds to the number
of independently allocatable registers. Relatedly, I'm still debugging
some allocation failures where overlapping tuples seem to not be
handled correctly.

The test changes are mostly noise. There are a handful of x86 tests
that look like regressions with an additional spill, and a handful
that now avoid a spill. The worst looking regression is likely
test/Thumb2/mve-vld4.ll which introduces a few additional
spills. test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll
shows a massive improvement by completely eliminating a large number
of spills inside a loop.
 		2021-09-14 21:00:29 -04:00
..
GlobalISel
…
intrinsics
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rvv RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
add-before-shl.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
add-imm.ll [RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns. 2021-08-18 11:07:11 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll [RISCV][test] Add more tests for (mul (add x, c1), c2) 2021-09-02 17:30:03 +08:00
addrspacecast.ll [RISCV] Assume no-op addrspacecasts by default 2020-12-18 21:03:37 +00:00
aext-to-sext.ll [RISCV] Protect the SHL/SRA/SRL handlers in LowerOperation against being called for an illegal i32 shift amount. 2021-06-29 09:45:13 -07:00
align-loops.ll [CodeGen] Add -align-loops 2021-08-04 12:45:18 -07:00
align.ll
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alloca.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
alu8.ll Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions." 2021-06-27 10:33:43 -07:00
alu16.ll [RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64. 2021-04-11 13:59:51 -07:00
alu32.ll [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64. 2021-08-26 10:20:19 -07:00
alu64.ll [RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32. 2020-11-25 21:57:48 -08:00
analyze-branch.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
arith-with-overflow.ll
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atomic-cmpxchg-flag.ll
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atomic-cmpxchg.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
atomic-fence.ll
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atomic-load-store.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
atomic-rmw.ll Allow rematerialization of virtual reg uses 2021-08-24 11:09:02 -07:00
atomic-signext.ll Allow rematerialization of virtual reg uses 2021-08-24 11:09:02 -07:00
attributes.ll [RISCV] Update the version number to v0.10 for vector. 2021-01-30 07:20:05 +08:00
blockaddress.ll [RISCV] Fix inaccurate annotations on PseudoBRIND 2020-08-21 11:38:42 +01:00
branch-relaxation.ll [RISCV] Indirect branch generation in position independent code 2020-08-17 13:09:26 +01:00
branch.ll [RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0) 2021-03-15 11:32:43 -07:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
byval.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
callee-saved-fpr32s.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
callee-saved-fpr64s.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
callee-saved-gprs.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-half.ll [RISCV] Improve constant materialization for stores of i16 or i32 negative constants. 2021-08-18 10:25:12 -07:00
calling-conv-ilp32-ilp32f-common.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-ilp32.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-ilp32d.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-lp64-lp64f-common.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
calling-conv-lp64.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-rv32f-ilp32.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-sext-zext.ll [RISCV] Don't print zext.b alias. 2021-01-05 10:41:08 -08:00
calling-conv-vector-float.ll [RISCV] Fix a crash when lowering split float arguments 2021-07-22 09:55:26 +01:00
calls.ll [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions. 2021-07-13 09:46:21 -07:00
cmp-bool.ll [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1) 2020-07-15 07:34:22 +00:00
codemodel-lowering.ll [RISCV] Fix inaccurate annotations on PseudoBRIND 2020-08-21 11:38:42 +01:00
compress-float.ll
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compress-inline-asm.ll
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compress.ll [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
copy-frameindex.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
copysign-casts.ll [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64. 2021-08-26 10:20:19 -07:00
disable-tail-calls.ll
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disjoint.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
div.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
double-arith.ll [RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd 2020-11-25 15:07:34 -08:00
double-bitmanip-dagcombines.ll [RISCV] Improve 64-bit integer materialization for some cases. 2021-04-01 09:12:52 -07:00
double-br-fcmp.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
double-calling-conv.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
double-convert.ll [RISCV] Support FP_TO_S/UINT_SAT for i32 and i64. 2021-08-07 16:06:00 -07:00
double-fcmp.ll [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO. 2021-01-12 10:45:03 -08:00
double-frem.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
double-imm.ll
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double-intrinsics.ll [RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno 2021-07-06 11:43:22 -07:00
double-isnan.ll [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
double-mem.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
double-previous-failure.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
double-select-fcmp.ll [RISCV] Optimize select_cc after fp compare expansion 2021-01-14 13:41:40 -08:00
double-stack-spill-restore.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
dwarf-eh.ll
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elf-preemption.ll [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local 2021-05-11 11:29:45 -07:00
exception-pointer-register.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
fastcc-float.ll [RISCV] Fix a crash when lowering split float arguments 2021-07-22 09:55:26 +01:00
fastcc-int.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
fixups-diff.ll test: clean up some of the RISCV tests (NFC) 2021-06-17 09:51:09 -07:00
fixups-relax-diff.ll test: clean up some of the RISCV tests (NFC) 2021-06-17 09:51:09 -07:00
float-arith.ll [RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd 2020-11-25 15:07:34 -08:00
float-bit-preserving-dagcombines.ll [RISCV] Improve 64-bit integer materialization for some cases. 2021-04-01 09:12:52 -07:00
float-bitmanip-dagcombines.ll
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float-br-fcmp.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
float-convert.ll [RISCV] Support FP_TO_S/UINT_SAT for i32 and i64. 2021-08-07 16:06:00 -07:00
float-fcmp.ll [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO. 2021-01-12 10:45:03 -08:00
float-frem.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
float-imm.ll
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float-intrinsics.ll [RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno 2021-07-06 11:43:22 -07:00
float-isnan.ll [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
float-mem.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
float-select-fcmp.ll [RISCV] Optimize select_cc after fp compare expansion 2021-01-14 13:41:40 -08:00
flt-rounds.ll
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fold-addi-loadstore.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
fp-imm.ll
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fp16-promote.ll [RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat. 2021-04-01 12:41:57 -07:00
fp128.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
fpenv.ll [RISCV] Custom lowering of SET_ROUNDING 2021-04-22 15:04:55 +07:00
frame-info.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
frame.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
frameaddr-returnaddr.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
get-register-invalid.ll
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get-register-noreserve.ll
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get-register-reserve.ll
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get-setcc-result-type.ll
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ghccc-rv32.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
ghccc-rv64.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
half-arith.ll [RISCV] Add additional half precision fnmadd/fnmsub tests with an fneg on the second operand instead of the first. 2020-12-02 21:13:42 -08:00
half-bitmanip-dagcombines.ll [RISCV] Add optimizations for FMV_X_ANYEXTH similar to FMV_X_ANYEXTW_RV64. 2021-08-08 18:30:48 -07:00
half-br-fcmp.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
half-convert.ll [RISCV] Support FP_TO_S/UINT_SAT for i32 and i64. 2021-08-07 16:06:00 -07:00
half-fcmp.ll [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO. 2021-01-12 10:45:03 -08:00
half-imm.ll [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
half-intrinsics.ll [RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno 2021-07-06 11:43:22 -07:00
half-isnan.ll [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
half-mem.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
half-select-fcmp.ll [RISCV] Optimize select_cc after fp compare expansion 2021-01-14 13:41:40 -08:00
hoist-global-addr-base.ll [RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0) 2021-03-15 11:32:43 -07:00
i32-icmp.ll
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imm-cse.ll
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imm.ll [RISCV] Improve constant materialization for stores of i16 or i32 negative constants. 2021-08-18 10:25:12 -07:00
indirectbr.ll [RISCV] Fix inaccurate annotations on PseudoBRIND 2020-08-21 11:38:42 +01:00
init-array.ll
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inline-asm-S-constraint.ll [RISCV] Support machine constraint "S" 2021-07-13 09:30:09 -07:00
inline-asm-abi-names.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
inline-asm-clobbers.ll
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inline-asm-d-abi-names.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
inline-asm-d-constraint-f.ll
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inline-asm-f-abi-names.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
inline-asm-f-constraint-f.ll
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inline-asm-i-constraint-i1.ll
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inline-asm-invalid.ll
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inline-asm.ll [MC][RISCV] Set UseIntegratedAssembler to true 2020-07-12 21:04:48 -07:00
interrupt-attr-args-error.ll
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interrupt-attr-callee.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
interrupt-attr-invalid.ll
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interrupt-attr-nocall.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
interrupt-attr-ret-error.ll
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interrupt-attr.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
jumptable.ll [CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchInst to honor isSExtCheaperThanZExt. 2021-06-23 15:38:11 -07:00
large-stack.ll [RISCV] remove redundant instruction when eliminate frame index 2021-03-21 18:54:00 +08:00
legalize-fneg.ll
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lit.local.cfg
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lsr-legaladdimm.ll
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machineoutliner-jumptable.mir [RISCV] Fix Machine Outliner jump table handling. 2021-09-09 07:32:30 +02:00
machineoutliner.mir
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mattr-invalid-combination.ll
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mem.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
mem64.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
mir-target-flags.ll [TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm 2020-12-05 14:54:37 -08:00
module-target-abi.ll
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module-target-abi2.ll
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mul.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
musttail-call.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
neg-abs.ll [RISCV][NFC] Increase test coverage of Zbt extension 2021-01-18 17:30:35 +00:00
nomerge.ll
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option-nopic.ll
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option-norelax.ll
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option-norvc.ll
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option-pic.ll
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option-relax.ll
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option-rvc.ll
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out-of-reach-emergency-slot.mir [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer 2021-01-23 09:10:03 +00:00
overflow-intrinsic-optimizations.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
patchable-function-entry.ll Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" 2021-05-29 15:11:37 +01:00
pic-models.ll Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" 2020-07-14 11:15:01 +01:00
pr40333.ll
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pr51206.ll [RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop. 2021-07-28 09:05:45 -07:00
prefetch.ll
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readcyclecounter.ll
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rem.ll [RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2) 2021-07-20 08:53:55 -07:00
remat.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
reserved-reg-errors.ll
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reserved-regs.ll
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rotl-rotr.ll
…
rv32e.ll
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rv32i-rv64i-float-double.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
rv32i-rv64i-half.ll Allow rematerialization of virtual reg uses 2021-08-24 11:09:02 -07:00
rv32zba.ll [RISCV][test] Add tests for optimization with SH*ADD in the zba extension 2021-09-02 17:30:03 +08:00
rv32zbb-intrinsic.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv32zbb-zbp.ll [RISCV] Fix the check prefixes in some B extension tests. NFC 2021-08-25 14:26:51 -07:00
rv32zbb.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
rv32zbc-intrinsic.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv32zbe-intrinsic.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv32zbp-intrinsic.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv32zbp.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
rv32zbr.ll [RISCV] Add IR intrinsic for Zbr extension 2021-04-02 10:58:45 -07:00
rv32zbs.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv32zbt.ll [RISCV] Fix the check prefixes in some B extension tests. NFC 2021-08-25 14:26:51 -07:00
rv64-large-stack.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
rv64d-double-convert.ll [RISCV] Custom lower (i32 (fptoui/fptosi X)). 2021-07-24 10:50:43 -07:00
rv64f-float-convert.ll [RISCV] Custom lower (i32 (fptoui/fptosi X)). 2021-07-24 10:50:43 -07:00
rv64f-half-convert.ll [RISCV] Custom lower (i32 (fptoui/fptosi X)). 2021-07-24 10:50:43 -07:00
rv64i-complex-float.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
rv64i-demanded-bits.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64i-double-softfloat.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
rv64i-exhaustive-w-insts.ll [RISCV] Add Zba command line to rv64i-exhaustive-w-insts.ll 2021-09-02 08:36:27 -07:00
rv64i-single-softfloat.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64m-exhaustive-w-insts.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64m-w-insts-legalization.ll Revert "[BPI] Improve static heuristics for integer comparisons" 2020-08-17 20:44:33 +02:00
rv64zba.ll [RISCV] Teach instruction selection to elide sext.w in some cases. 2021-09-02 07:54:34 -07:00
rv64zbb-intrinsic.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv64zbb-zbp.ll [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64. 2021-08-26 10:20:19 -07:00
rv64zbb.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
rv64zbc-intrinsic.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv64zbe-intrinsic.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv64zbp-intrinsic.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv64zbp.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
rv64zbr.ll [RISCV] Add IR intrinsic for Zbr extension 2021-04-02 10:58:45 -07:00
rv64zbs.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
rv64zbt.ll [RISCV] Improve check prefixes in B extension tests. NFC 2021-08-12 12:41:40 -07:00
sadd_sat.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
sadd_sat_plus.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
saverestore.ll [RISCV] Don't emit save-restore call if function is a interrupt handler 2021-04-16 12:54:47 +08:00
scalable-vector-struct.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
sdata-limit-0.ll
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sdata-limit-4.ll
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sdata-limit-8.ll
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sdata-local-sym.ll
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select-and.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
select-bare.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
select-binop-identity.ll [RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y)) 2021-08-10 09:02:56 -07:00
select-cc.ll [RISCV] Support RISCVISD::SELECT_CC in ComputeNumSignBitsForTargetNode. 2021-08-13 18:00:09 -07:00
select-const.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
select-constant-xor.ll [DAG] Fix GT -> GE condition when creating SetCC 2021-09-08 12:41:51 +01:00
select-optimize-multiple.ll [RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate. 2021-01-22 14:51:22 -08:00
select-optimize-multiple.mir [RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC 2021-08-08 17:25:37 -07:00
select-or.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
setcc-logic.ll [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. 2021-08-18 10:44:25 -07:00
sext-zext-trunc.ll [TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper 2021-01-25 16:37:21 -08:00
shadowcallstack.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
shift-masked-shamt.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
shifts.ll [RISCV] Disable use of i128 shift libcalls on RV32. 2021-09-08 14:26:07 -07:00
shrinkwrap.ll [RISCV] Improve shrink wrap test (NFC) 2021-09-02 12:14:04 -05:00
spill-fpr-scalar.ll [RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant. 2021-07-23 09:12:05 -07:00
split-offsets.ll [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. 2021-08-18 10:44:25 -07:00
split-sp-adjust.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
srem-lkk.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
srem-seteq-illegal-types.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
srem-vector-lkk.ll Allow rematerialization of virtual reg uses 2021-08-24 11:09:02 -07:00
ssub_sat.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
ssub_sat_plus.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
stack-realignment-with-variable-sized-objects.ll [RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates. 2021-01-15 11:14:14 -08:00
stack-realignment.ll [RISCV] remove redundant instruction when eliminate frame index 2021-03-21 18:54:00 +08:00
stack-slot-size.ll [RISCV] Fix stack slot for argument types (Bug 49500) 2021-04-29 09:10:48 +01:00
stack-store-check.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
subtarget-features-std-ext.ll
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tail-calls.ll [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions. 2021-07-13 09:46:21 -07:00
target-abi-invalid.ll
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target-abi-valid.ll
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thread-pointer.ll
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tls-models.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
uadd_sat.ll [RISCV] Improve i32 UADDSAT/USUBSAT on RV64. 2021-03-16 07:44:06 -07:00
uadd_sat_plus.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
umulo-128-legalisation-lowering.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
urem-lkk.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
urem-seteq-illegal-types.ll [RISCV] Select vector shl by 1 to a vector add. 2021-07-27 10:57:28 -07:00
urem-vector-lkk.ll Allow rematerialization of virtual reg uses 2021-08-24 11:09:02 -07:00
usub_sat.ll [RISCV] Improve i32 UADDSAT/USUBSAT on RV64. 2021-03-16 07:44:06 -07:00
usub_sat_plus.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
vararg.ll [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. 2021-08-18 10:44:25 -07:00
vec3-setcc-crash.ll Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions." 2021-06-27 10:33:43 -07:00
vector-abi.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
verify-instr.mir
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wide-mem.ll
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xaluo.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
zext-with-load-is-free.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
zfh-imm.ll [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00