forked from OSchip/llvm-project
30 lines
1.1 KiB
LLVM
30 lines
1.1 KiB
LLVM
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
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; Test correct code generation for medium and large code model
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; for loading and storing a weak variable
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@wi = weak global i32 0, align 4
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define signext i32 @test_weak() nounwind {
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entry:
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%0 = load i32, i32* @wi, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @wi, align 4
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ret i32 %0
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}
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; CHECK-LABEL: test_weak:
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; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
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; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
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; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
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; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha
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; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]])
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; CHECK: stw {{[0-9]+}}, 0([[REG4]])
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; CHECK: .section .toc
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; CHECK: .LC[[TOCNUM]]:
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; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}
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