James Y Knight 148a6469dc Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. ... Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025		2016-06-17 18:11:48 +00:00
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ARM	ARM: use a pseudo-instruction for cmpxchg at -O0.	2016-04-18 21:48:55 +00:00
SPARC	Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass.	2016-06-17 18:11:48 +00:00
X86	[IR] Extend cmpxchg to allow pointer type operands	2016-02-19 00:06:41 +00:00