forked from OSchip/llvm-project
75 lines
2.0 KiB
LLVM
75 lines
2.0 KiB
LLVM
; Test extensions of f32 to f64.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
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; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Check register extension.
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define double @f1(float %val) {
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; CHECK-LABEL: f1:
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; CHECK: ldebr %f0, %f0
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; CHECK: br %r14
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%res = fpext float %val to double
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ret double %res
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}
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; Check the low end of the LDEB range.
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define double @f2(float *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: ldeb %f0, 0(%r2)
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; CHECK: br %r14
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%val = load float , float *%ptr
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%res = fpext float %val to double
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ret double %res
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}
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; Check the high end of the aligned LDEB range.
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define double @f3(float *%base) {
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; CHECK-LABEL: f3:
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; CHECK: ldeb %f0, 4092(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float, float *%base, i64 1023
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%val = load float , float *%ptr
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%res = fpext float %val to double
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ret double %res
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define double @f4(float *%base) {
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; CHECK-LABEL: f4:
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; CHECK: aghi %r2, 4096
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; CHECK: ldeb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float, float *%base, i64 1024
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%val = load float , float *%ptr
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%res = fpext float %val to double
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ret double %res
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}
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; Check negative displacements, which also need separate address logic.
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define double @f5(float *%base) {
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; CHECK-LABEL: f5:
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; CHECK: aghi %r2, -4
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; CHECK: ldeb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float, float *%base, i64 -1
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%val = load float , float *%ptr
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%res = fpext float %val to double
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ret double %res
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}
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; Check that LDEB allows indices.
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define double @f6(float *%base, i64 %index) {
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; CHECK-LABEL: f6:
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; CHECK: sllg %r1, %r3, 2
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; CHECK: ldeb %f0, 400(%r1,%r2)
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; CHECK: br %r14
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%ptr1 = getelementptr float, float *%base, i64 %index
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%ptr2 = getelementptr float, float *%ptr1, i64 100
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%val = load float , float *%ptr2
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%res = fpext float %val to double
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ret double %res
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}
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