Matt Arsenault 5207545a86 GlobalISel: IRTranslate minimum of pointer sizes on memcpy ... I forgot to squash this with 0b7f6cc71a		2020-08-26 20:10:00 -04:00
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AArch64	GlobalISel: Add generic instructions for memory intrinsics	2020-08-26 20:08:45 -04:00
AMDGPU	GlobalISel: IRTranslate minimum of pointer sizes on memcpy	2020-08-26 20:10:00 -04:00
ARC	[ARC] Fix CodeGen/ARC/brcc.ll	2020-08-15 19:33:35 -07:00
ARM	[ARM][MachineOutliner] Add default mode.	2020-08-20 09:25:33 +02:00
AVR	…
BPF	BPF: add a SimplifyCFG IR pass during generic Scalar/IPO optimization	2020-08-06 13:16:00 -07:00
Generic	[Tests] Be consistent w/definition of statepoint-example	2020-08-14 20:45:48 -07:00
Hexagon	[Hexagon] Implement llvm.masked.load and llvm.masked.store for HVX	2020-08-26 13:10:22 -05:00
Inputs	…
Lanai	…
MIR	[AMDGPU] Reorganize GCN subtarget features for unaligned access	2020-08-21 12:26:31 +02:00
MSP430	…
Mips	GlobalISel: Add generic instructions for memory intrinsics	2020-08-26 20:08:45 -04:00
NVPTX	[NVPTX] Fix typo in lit test	2020-08-17 16:02:11 -04:00
PowerPC	[XCOFF][AIX] Support relocation generation for large code model	2020-08-26 17:12:28 +00:00
RISCV	[RISCV] Fix inaccurate annotations on PseudoBRIND	2020-08-21 11:38:42 +01:00
SPARC	[llvm-readobj] Update tests because of changes in llvm-readobj behavior	2020-07-20 10:39:04 +01:00
SystemZ	Revert "[BPI] Improve static heuristics for integer comparisons"	2020-08-17 20:44:33 +02:00
Thumb	…
Thumb2	[llvm] [Thumb2] Test unusual length for active lane mask	2020-08-26 12:20:35 -07:00
VE	[VE] Support f128	2020-08-17 17:26:52 +09:00
WebAssembly	[SelectionDAG] Handle non-power-of-2 bitwidths in expandROT	2020-08-26 09:20:46 +01:00
WinCFGuard	…
WinEH	…
X86	GlobalISel: Add generic instructions for memory intrinsics	2020-08-26 20:08:45 -04:00
XCore	…