forked from OSchip/llvm-project
816542ceb3
The new experimental reduction intrinsics can now be used, so I'm enabling this for AArch64. We will need this for SVE anyway, so it makes sense to do this for NEON reductions as well. The existing code to match shufflevector patterns are replaced with a direct lowering of the reductions to AArch64-specific nodes. Tests updated with the new, simpler, representation. Differential Revision: https://reviews.llvm.org/D32247 llvm-svn: 302678 |
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| .. | ||
| aarch64-predication.ll | ||
| aarch64-unroll.ll | ||
| arbitrary-induction-step.ll | ||
| arm64-unroll.ll | ||
| backedge-overflow.ll | ||
| deterministic-type-shrinkage.ll | ||
| gather-cost.ll | ||
| induction-trunc.ll | ||
| interleaved-vs-scalar.ll | ||
| interleaved_cost.ll | ||
| lit.local.cfg | ||
| loop-vectorization-factors.ll | ||
| max-vf-for-interleaved.ll | ||
| pr31900.ll | ||
| predication_costs.ll | ||
| reduction-small-size.ll | ||
| sdiv-pow2.ll | ||
| smallest-and-widest-types.ll | ||
| type-shrinkage-insertelt.ll | ||