forked from OSchip/llvm-project
a228c46c2a
Summary: The floating-point and SSE registers could be present in the elf-core file in the note NT_FPREGSET for 64 bit ones, and in the note NT_PRXFPREG for 32 bit ones. The entire note is a binary blob matching the layout of the x87 save area that gets generated by the FXSAVE instruction (see Intel developers manual for more information). This CL mainly modifies the RegisterRead function in RegisterContextPOSIXCore_x86_64 for it to return the correct data both for GPR and FPR/SSE registers, and return false (meaning "this register is not available") for other registers. I added a test to TestElfCore.py that tests reading FPR/SSE registers both from a 32 and 64 bit elf-core file and I have inluded the source which I used to generate the core files. I tried to also add support for the AVX registers, because this info could also be present in the elf-core file (note NT_X86_XSTATE - that is the result of the newer XSAVE instruction). Parsing the contents from the file is easy. The problem is that the ymm registers are split into two halves and they are in different places in the note. For making this work one would either make a "hacky" approach, because there won't be any other way with the current state of the register contexts - they assume that "this register is of size N and at offset M" and don't have the notion of discontinuos registers. Reviewers: labath Subscribers: emaste, lldb-commits Differential Revision: https://reviews.llvm.org/D26300 llvm-svn: 287506 |
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| pre_kill_hook | ||
| support | ||
| test | ||
| test_event | ||
| .clang-format | ||
| __init__.py | ||