forked from OSchip/llvm-project
35 lines
1.2 KiB
ArmAsm
35 lines
1.2 KiB
ArmAsm
# REQUIRES: ppc
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# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s -o %t.o
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# RUN: ld.lld %t.o -o %t
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# RUN: llvm-readelf -S -l %t | FileCheck --check-prefix=SEC %s
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# RUN: llvm-objdump -d %t | FileCheck --check-prefix=DIS %s
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# SEC: Name Type Address Off Size ES Flg Lk Inf Al
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# SEC: .tdata PROGBITS 0000000010020300 000300 000001 00 WAT 0 0 1
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# SEC: .tbss NOBITS 0000000010020400 000301 000008 00 WAT 0 0 256
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# SEC: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
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# SEC: TLS 0x000300 0x0000000010020300 0x0000000010020300 0x000001 0x000108 R 0x100
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## We currently have a hack in Writer.cpp:fixSectionAlignments() to force
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## p_vaddr(PT_TLS)%p_align(PT_TLS)=0, to work around bugs in some dynamic loaders.
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## p_vaddr rounded down to p_align has TP offset -0x7000.
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## The first address of PT_TLS (p_vaddr) has TP offset (p_vaddr%p_align - 0x7000).
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## Once we delete the hack, it is likely p_vaddr%p_align != 0.
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## a@tprel = st_value(a) + p_vaddr%p_align - 0x7000 = .tbss-.tdata + p_vaddr%p_align - 0x7000
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## = 0x10020400-0x10020300 + 0 - 0x7000 = -28416
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# DIS: ld 3, -28416(13)
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ld 3, a@tprel(13)
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.section .tdata,"awT"
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.byte 0
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.section .tbss,"awT"
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.p2align 8
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a:
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.quad 0
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