forked from OSchip/llvm-project
54 lines
1.7 KiB
ArmAsm
54 lines
1.7 KiB
ArmAsm
// REQUIRES: aarch64
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// RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
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// RUN: ld.lld --image-base=0x10000000 %t.o -o %t
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// RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
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// Check that the ARM 64-bit ABI rules for undefined weak symbols are applied.
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// Branch instructions are resolved to the next instruction. Undefined
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// Symbols in relative are resolved to the place so S - P + A = A.
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// We place the image-base at 0x10000000 to test that a range extensions thunk
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// is not generated.
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.weak target
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.text
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.global _start
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_start:
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// R_AARCH64_JUMP26
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b target
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// R_AARCH64_CALL26
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bl target
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// R_AARCH64_CONDBR19
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b.eq target
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// R_AARCH64_TSTBR14
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cbz x1, target
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// R_AARCH64_ADR_PREL_LO21
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adr x0, target
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// R_AARCH64_ADR_PREL_PG_HI21
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adrp x0, target
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// R_AARCH64_LD_PREL_LO19
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ldr x8, target
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// R_AARCH64_PREL32
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.word target - .
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// R_AARCH64_PREL64
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.xword target - .
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// R_AARCH64_PREL16
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.hword target - .
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// R_AARCH64_PLT32
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.word target@PLT - .
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// CHECK: Disassembly of section .text:
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// CHECK-EMPTY:
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// CHECK-NEXT: 0000000010010120 <_start>:
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// CHECK-NEXT: 10010120: b 0x10010124
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// CHECK-NEXT: 10010124: bl 0x10010128
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// CHECK-NEXT: 10010128: b.eq 0x1001012c
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// CHECK-NEXT: 1001012c: cbz x1, 0x10010130
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// CHECK-NEXT: 10010130: adr x0, #0
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// CHECK-NEXT: 10010134: adrp x0, 0x10010000
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// CHECK-NEXT: 10010138: ldr x8, 0x10010138
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// CHECK: 1001013c: 00 00 00 00 .word 0x00000000
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// CHECK-NEXT: 10010140: 00 00 00 00 .word 0x00000000
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// CHECK-NEXT: 10010144: 00 00 00 00 .word 0x00000000
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// CHECK-NEXT: 10010148: 00 00 00 00 .word 0x00000000
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// CHECK-NEXT: 1001014c: 00 00 .short 0x0000
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