forked from OSchip/llvm-project
64 lines
1.8 KiB
ArmAsm
64 lines
1.8 KiB
ArmAsm
# REQUIRES: aarch64
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# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %s -o %t.o
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# RUN: ld.lld %t.o -o %t
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# RUN: llvm-objdump --no-show-raw-insn -d %t | FileCheck %s
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# RUN: llvm-readobj --symbols %t | FileCheck --check-prefix=CHECK-SYM %s
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## Test the local exec relocations that map to:
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## R_AARCH64_TLSLE_MOVW_TPREL_G2
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## R_AARCH64_TLSLE_MOVW_TPREL_G1
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## R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
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## R_AARCH64_TLSLE_MOVW_TPREL_G0
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## R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
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## They calculate the same value as the other TPREL relocations, namely the
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## offset from the thread pointer TP. The G0, G1 and G2 refer to partitions
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## of the result with G2 bits [47:32], G1 bits [31:16] and G0 bits [15:0]
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## the NC variant does not check for overflow.
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## In AArch64 the structure of the TLS at runtime is:
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## | TCB | Alignment Padding | TLS Block |
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## With TP pointing to the start of the TCB. All offsets will be positive.
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.text
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## Access variable in first partition
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movz x0, #:tprel_g0:v0
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## TCB + 0 == 16
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# CHECK: mov x0, #16
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# CHECK-SYM: Name: v0
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# CHECK-SYM-NEXT: Value: 0x0
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## Access variable in second partition
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movz x0, #:tprel_g1:v1
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movk x0, #:tprel_g0_nc:v1
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## TCB + 65536 across movz and movk
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# CHECK-NEXT: mov x0, #65536
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# CHECK-NEXT: movk x0, #16
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# CHECK-SYM: Name: v1
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# CHECK-SYM-NEXT: Value: 0x10000
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## Access variable in third partition
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movz x0, #:tprel_g2:v2
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movk x0, #:tprel_g1_nc:v2
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movk x0, #:tprel_g0_nc:v2
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## TCB + 65536 + 4294967296 across movz and 2 movk instructions
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# CHECK-NEXT: mov x0, #4294967296
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# CHECK-NEXT: movk x0, #1, lsl #16
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# CHECK-NEXT: movk x0, #16
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# CHECK-SYM: Name: v2
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# CHECK-SYM-NEXT: Value: 0x100010000
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.section .tbss,"awT",@nobits
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.balign 16
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v0:
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.quad 0
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.space 0x10000 - 8
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v1:
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.quad 0
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.space 0x100000000 - 8
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v2:
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.quad 0
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