forked from OSchip/llvm-project
26 lines
1.0 KiB
LLVM
26 lines
1.0 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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;
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; Test for bug in misched memory dependency calculation.
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: misched_bug:%bb.0 entry
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; CHECK: SU(2): %2:gpr32 = LDRWui %0:gpr64common, 1 :: (load 4 from %ir.ptr1_plus1)
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; CHECK: Successors:
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; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2
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; CHECK-NEXT: SU(4): Ord Latency=0
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; CHECK: SU(3): STRWui $wzr, %0:gpr64common, 0 :: (store 4 into %ir.ptr1)
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; CHECK: Successors:
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; CHECK: SU(4): Ord Latency=0
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; CHECK: SU(4): STRWui $wzr, %1:gpr64common, 0 :: (store 4 into %ir.ptr2)
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; CHECK: SU(5): $w0 = COPY %2
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; CHECK: ** ScheduleDAGMI::schedule picking next node
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define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
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entry:
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%ptr1_plus1 = getelementptr inbounds i32, i32* %ptr1, i64 1
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%val1 = load i32, i32* %ptr1_plus1, align 4
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store i32 0, i32* %ptr1, align 4
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store i32 0, i32* %ptr2, align 4
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ret i32 %val1
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}
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