Anton Afanasyev 1f3e35b6d1 [AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG ... Add `shl` instruction to the DAG post-dominated by `trunc`, allowing TruncInstCombine to reduce bitwidth of expressions containing left shifts. The only thing we need to check is that the target bitwidth must be wider than the maximal shift amount: https://alive2.llvm.org/ce/z/AwArqu Part of https://reviews.llvm.org/D107766 Differential Revision: https://reviews.llvm.org/D108091		2021-08-17 12:44:37 +03:00
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AggressiveInstCombine.cpp	[NewPM] Don't mark AA analyses as preserved	2021-05-18 13:49:03 -07:00
AggressiveInstCombineInternal.h	…
CMakeLists.txt	…
TruncInstCombine.cpp	[AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG	2021-08-17 12:44:37 +03:00