| .. |
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autohvx
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[Hexagon] Implement HVX codegen for vector shifts
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2018-01-31 20:49:24 +00:00 |
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intrinsics
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[Hexagon] Fix operand-swapping PatFrag for atomic stores
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2017-12-15 20:13:57 +00:00 |
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loop-idiom
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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vect
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[Hexagon] SETEQ and SETNE are valid integer condition codes
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2018-01-25 18:07:27 +00:00 |
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Atomics.ll
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[Hexagon] Handle expansion of cmpxchg
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2016-06-22 16:07:10 +00:00 |
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BranchPredict.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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NVJumpCmp.ll
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[Hexagon] Add NewValueJump support for C4_cmpneq, C4_cmplte, C4_cmplteu
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2015-12-08 16:28:32 +00:00 |
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PR33749.ll
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[Hexagon] Reorganize and update instruction patterns
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2017-10-20 19:33:12 +00:00 |
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SUnit-boundary-prob.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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absaddr-store.ll
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[Hexagon] Fix printing the address operand of S2_storerinewabs
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2016-04-19 20:20:33 +00:00 |
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absimm.ll
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[Hexagon] Fixing store instructions and reenabling a few more tests.
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2015-11-10 00:22:00 +00:00 |
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addaddi.ll
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[Hexagon] Add extra pattern for S4_addaddi
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2017-10-23 19:07:50 +00:00 |
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adde.ll
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[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
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2017-03-09 16:29:30 +00:00 |
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addh-sext-trunc.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addh-shifted.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addh.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addr-calc-opt.ll
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[Hexagon] Improve balancing of address calculation
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2016-07-29 15:15:35 +00:00 |
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addrmode-globoff.mir
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[Hexagon] Generate proper offset in opt-addr-mode
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2017-04-19 15:15:51 +00:00 |
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addrmode-indoff.ll
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[Hexagon] Reorganize and update instruction patterns
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2017-10-20 19:33:12 +00:00 |
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addrmode-keepdeadphis.mir
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[Hexagon] Keep all phi nodes when building DFG in addr-mode-opt
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2017-06-29 15:55:59 +00:00 |
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addrmode-rr-to-io.mir
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[Hexagon] Fix store conversion from rr to io in optimize addressing modes
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2017-10-19 16:59:22 +00:00 |
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adjust-latency-stackST.ll
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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2018-01-19 17:13:12 +00:00 |
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alu64.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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always-ext.ll
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[Hexagon] Fixing load instruction parsing and reenabling tests.
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2015-11-10 00:02:27 +00:00 |
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anti-dep-partial.mir
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Move .mir tests to appropriate directories
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2016-12-09 19:08:15 +00:00 |
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args.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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ashift-left-right.ll
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…
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avoid-predspill-calleesaved.ll
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[Hexagon] Start using regmasks on calls
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2017-02-17 22:14:51 +00:00 |
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avoid-predspill.ll
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[Hexagon] Optimize stack slot spills
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2016-02-12 22:53:35 +00:00 |
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bank-conflict-load.mir
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[Hexagon] Check for potential bank conflicts in post-RA scheduling
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2017-08-28 18:36:21 +00:00 |
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barrier-flag.ll
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…
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base-offset-addr.ll
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…
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base-offset-post.ll
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…
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bit-bitsplit-at.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-bitsplit-src.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-bitsplit.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-eval.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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bit-ext-sat.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-extract-off.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-extract.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-extractu-half.ll
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[Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword
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2016-01-14 21:59:22 +00:00 |
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bit-gen-rseq.ll
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MachinePipeliner pass that implements Swing Modulo Scheduling
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2016-07-29 16:44:44 +00:00 |
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bit-has.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-loop-rc-mismatch.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-loop.ll
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[Hexagon] Bit-based instruction simplification
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2015-10-20 22:57:13 +00:00 |
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bit-phi.ll
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[Hexagon] Do not insert instructions before PHI nodes
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2017-03-07 14:20:19 +00:00 |
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bit-rie.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-skip-byval.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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bit-validate-reg.ll
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[Hexagon] Generate extract instructions more aggressively
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2017-02-28 23:27:33 +00:00 |
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bit-visit-flowq.ll
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[Hexagon] Clear the flow queue after visiting a single instruction
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2016-09-13 14:36:55 +00:00 |
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bitconvert-vector.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bitmanip.ll
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[Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE
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2017-02-23 15:02:09 +00:00 |
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block-addr.ll
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[Hexagon] Reorganize and update instruction patterns
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2017-10-20 19:33:12 +00:00 |
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block-ranges-nodef.ll
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[Hexagon] Properly close live range in HexagonBlockRanges ---add testcase
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2016-04-22 17:30:13 +00:00 |
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branch-folder-hoist-kills.mir
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
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2017-12-07 10:40:31 +00:00 |
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branch-non-mbb.ll
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[Hexagon] Handle branches with non-mbb operands
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2016-01-14 15:05:27 +00:00 |
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branchfolder-insert-impdef.mir
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Insert IMPLICIT_DEFS for undef uses in tail merging
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2017-09-06 20:45:24 +00:00 |
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branchfolder-keep-impdef.ll
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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2018-01-19 17:13:12 +00:00 |
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brev_ld.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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brev_st.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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bugAsmHWloop.ll
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…
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build-vector-shuffle.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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build-vector-v4i8-zext.ll
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[Hexagon] Make sure to zero-extend bytes before building a vector
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2017-11-28 19:13:17 +00:00 |
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builtin-expect.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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builtin-prefetch-offset.ll
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[Hexagon] Add support for __builtin_prefetch
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2016-02-18 13:58:38 +00:00 |
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builtin-prefetch.ll
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[Hexagon] Add support for __builtin_prefetch
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2016-02-18 13:58:38 +00:00 |
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call-ret-i1.ll
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[Hexagon] Return the correct chain edge for i1 function calls
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2017-10-23 19:35:25 +00:00 |
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calling-conv-2.ll
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…
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callr-dep-edge.ll
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[ScheduleDAG] Make sure to process all def operands before any use operands
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2016-05-10 16:50:30 +00:00 |
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cext-check.ll
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[Hexagon] Simplify HexagonInstrInfo::isPredicable
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2016-05-16 16:56:10 +00:00 |
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cext-opt-basic.mir
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MIR: Print the register class or bank in vreg defs
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2017-10-24 18:04:54 +00:00 |
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cext-opt-numops.mir
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[Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cpp
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2017-10-27 18:52:28 +00:00 |
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cext-opt-range-assert.mir
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[Hexagon] Fix an incorrect assertion in HexagonConstExtenders
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2018-01-26 19:20:50 +00:00 |
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cext-opt-range-offset.mir
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[Hexagon] Account for negative offset when limiting max deviation
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2017-10-25 18:46:40 +00:00 |
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cext-opt-shifted-range.mir
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[Hexagon] Handle non-aligned offsets in globals in extender optimization
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2018-01-30 18:12:37 +00:00 |
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cext-valid-packet1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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cext-valid-packet2.ll
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…
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cext.ll
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…
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cexti16.ll
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…
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cfgopt-fall-through.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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cfi-late.ll
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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cfi-offset.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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checktabs.ll
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…
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circ-load-isel.ll
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[Hexagon] Remove dead nodes from SelectionDAG to avoid cycles
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2016-05-13 18:48:15 +00:00 |
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circ_ld.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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circ_ldd_bug.ll
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[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
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2017-11-30 12:12:19 +00:00 |
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circ_ldw.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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circ_st.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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clr_set_toggle.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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cmp-extend.ll
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…
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cmp-promote.ll
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…
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cmp-to-genreg.ll
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…
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cmp-to-predreg.ll
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…
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cmp.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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cmp_pred.ll
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…
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cmp_pred2.ll
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…
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cmp_pred_reg.ll
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…
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cmpb-dec-imm.ll
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[Hexagon] Add patterns for cmpb/cmph with immediate arguments
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2017-10-13 15:43:12 +00:00 |
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cmpb-eq.ll
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…
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cmpb_pred.ll
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…
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cmph-gtu.ll
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[Hexagon] Add patterns for cmpb/cmph with immediate arguments
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2017-10-13 15:43:12 +00:00 |
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combine.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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combine_ir.ll
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[Hexagon] Split double registers
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2015-10-16 20:38:54 +00:00 |
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common-gep-basic.ll
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…
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common-gep-icm.ll
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…
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common-gep-inbounds.ll
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[Hexagon] Run late copy propagation and dead code elimination passes
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2018-01-24 17:48:11 +00:00 |
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compound.ll
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[Hexagon] Start using regmasks on calls
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2017-02-17 22:14:51 +00:00 |
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const-pool-tf.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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const64.ll
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[Hexagon] Generate CONST64 when optimizing for size in copy-to-combine
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2016-01-15 14:08:31 +00:00 |
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constp-clb.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-combine-neg.ll
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[Hexagon] Implement buildVector32 and buildVector64 as utility functions
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2017-11-22 20:56:23 +00:00 |
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constp-ctb.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-extract.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-physreg.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-rewrite-branches.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-rseq.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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constp-vsplat.ll
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[Hexagon] Implement MI-level constant propagation
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2016-07-28 20:01:59 +00:00 |
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convert-to-dot-old.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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convert_const_i1_to_i8.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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convertdptoint.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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convertdptoll.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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convertsptoint.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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convertsptoll.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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copy-to-combine-dbg.ll
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[Hexagon] Check for block end when skipping debug instructions
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2016-08-24 22:36:35 +00:00 |
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csr-func-usedef.ll
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[Hexagon] Register save/restore functions do not follow regular conventions
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2016-04-25 17:49:44 +00:00 |
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ctor.ll
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…
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dadd.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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dead-store-stack.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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dmul.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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double.ll
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…
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doubleconvert-ieee-rnd-near.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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dsub.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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dualstore.ll
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…
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duplex-addi-global-imm.mir
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[Hexagon] Fix typo in a testcase
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2017-06-22 16:25:46 +00:00 |
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duplex.ll
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[CodeGen] Always use `printReg` to print registers in both MIR and debug
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2017-11-30 16:12:24 +00:00 |
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early-if-conversion-bug1.ll
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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2018-01-19 17:13:12 +00:00 |
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early-if-debug.mir
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[CodeGen] Always use `printReg` to print registers in both MIR and debug
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2017-11-30 16:12:24 +00:00 |
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early-if-merge-loop.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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early-if-phi-i1.ll
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[Hexagon] Add -march=hexagon to a testcase
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2017-03-21 16:59:40 +00:00 |
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early-if-spare.ll
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…
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early-if-vecpi.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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early-if-vecpred.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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early-if.ll
|
…
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eh_return.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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eliminate-pred-spill.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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expand-condsets-basic.ll
|
…
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expand-condsets-dead-bad.ll
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[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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expand-condsets-dead-pred.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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expand-condsets-def-undef.mir
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MIR: Print the register class or bank in vreg defs
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2017-10-24 18:04:54 +00:00 |
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expand-condsets-extend.ll
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[Hexagon] Deal with undefs when extending live intervals
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2016-09-01 13:59:35 +00:00 |
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expand-condsets-imm.mir
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MIR: Print the register class or bank in vreg defs
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2017-10-24 18:04:54 +00:00 |
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expand-condsets-impuse.mir
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MIR: Print the register class or bank in vreg defs
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2017-10-24 18:04:54 +00:00 |
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expand-condsets-pred-undef.ll
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[Hexagon] Teach mux expansion how to deal with undef predicates
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2016-04-22 16:47:01 +00:00 |
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expand-condsets-rm-reg.mir
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[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
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2017-11-30 12:12:19 +00:00 |
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expand-condsets-rm-segment.ll
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…
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expand-condsets-same-inputs.mir
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[Hexagon] Don't expand mux instructions with both sources identical
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2016-10-31 15:45:09 +00:00 |
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expand-condsets-undef.ll
|
…
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expand-condsets-undef2.ll
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[Hexagon] Check for empty live interval
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2016-08-19 14:29:43 +00:00 |
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expand-condsets-undefvni.ll
|
Missed a check for UndefVI in r306466
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2017-06-28 15:46:16 +00:00 |
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expand-vselect-kill.ll
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[Hexagon] Run late copy propagation and dead code elimination passes
|
2018-01-24 17:48:11 +00:00 |
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expand-vstorerw-undef.ll
|
[Hexagon] Allow construction of HVX vector predicates
|
2017-12-20 20:49:43 +00:00 |
|
expand-vstorerw-undef2.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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extload-combine.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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extract-basic.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fadd.ll
|
[Hexagon] Preclude non-memory test from being optimized away. NFC.
|
2017-07-05 13:08:03 +00:00 |
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fcmp.ll
|
…
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find-loop-instr.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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fixed-spill-mutable.ll
|
Fixed spill stack objects are mutable
|
2016-08-31 13:52:17 +00:00 |
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float-amode.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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float.ll
|
…
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floatconvert-ieee-rnd-near.ll
|
…
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fminmax.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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fmul.ll
|
[Hexagon] Preclude non-memory test from being optimized away. NFC.
|
2017-07-05 13:08:03 +00:00 |
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fpelim-basic.ll
|
[Hexagon] Implement frame pointer elimination with -fomit-frame-pointer
|
2017-06-30 21:21:40 +00:00 |
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frame-offset-overflow.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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fsel.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fsub.ll
|
[Hexagon] Preclude non-memory test from being optimized away. NFC.
|
2017-07-05 13:08:03 +00:00 |
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fusedandshift.ll
|
[Hexagon] Generate extract instructions more aggressively
|
2017-02-28 23:27:33 +00:00 |
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gp-plus-offset-load.ll
|
[Hexagon] Missed testcase update in r260895
|
2016-02-15 16:15:02 +00:00 |
|
gp-plus-offset-store.ll
|
…
|
|
|
gp-rel.ll
|
[Hexagon] Adding gp+ to the syntax of gp-relative instructions
|
2017-02-06 23:18:57 +00:00 |
|
hasfp-crash1.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
hasfp-crash2.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
hexagon_vector_loop_carried_reuse.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
hexagon_vector_loop_carried_reuse_constant.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
hvx-nontemporal.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
hwloop-cleanup.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
hwloop-const.ll
|
…
|
|
|
hwloop-crit-edge.ll
|
[LSR] Don't try and create post-inc expressions on non-rotated loops
|
2016-08-15 07:53:03 +00:00 |
|
hwloop-dbg.ll
|
[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
|
2016-04-15 15:57:41 +00:00 |
|
hwloop-le.ll
|
…
|
|
|
hwloop-loop1.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
hwloop-lt.ll
|
…
|
|
|
hwloop-lt1.ll
|
…
|
|
|
hwloop-missed.ll
|
…
|
|
|
hwloop-ne.ll
|
…
|
|
|
hwloop-noreturn-call.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
hwloop-ph-deadcode.ll
|
…
|
|
|
hwloop-pos-ivbump1.ll
|
…
|
|
|
hwloop-preh.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
hwloop-preheader.ll
|
…
|
|
|
hwloop-range.ll
|
…
|
|
|
hwloop-recursion.ll
|
…
|
|
|
hwloop-redef-imm.mir
|
[CodeGen] Unify MBB reference format in both MIR and debug output
|
2017-12-04 17:18:51 +00:00 |
|
hwloop-wrap.ll
|
…
|
|
|
hwloop-wrap2.ll
|
…
|
|
|
hwloop1.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
hwloop2.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
hwloop3.ll
|
…
|
|
|
hwloop4.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
hwloop5.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
i1_VarArg.ll
|
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
|
2015-11-25 20:30:59 +00:00 |
|
i8_VarArg.ll
|
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
|
2015-11-25 20:30:59 +00:00 |
|
i16_VarArg.ll
|
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
|
2015-11-25 20:30:59 +00:00 |
|
idxload-with-zero-offset.ll
|
…
|
|
|
ifcvt-common-kill.mir
|
[IfConversion] Remove kill flags from common instructions as well
|
2017-09-06 17:57:13 +00:00 |
|
ifcvt-diamond-bad.ll
|
Proper handling of diamond-like cases in if-conversion
|
2016-01-20 13:14:52 +00:00 |
|
ifcvt-diamond-bug-2016-08-26.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
ifcvt-edge-weight.ll
|
[CodeGen] Unify MBB reference format in both MIR and debug output
|
2017-12-04 17:18:51 +00:00 |
|
ifcvt-impuse-livein.mir
|
[IfConversion] More simple, correct dead/kill liveness handling
|
2017-09-14 15:53:11 +00:00 |
|
ifcvt-live-subreg.mir
|
[IfConversion] More simple, correct dead/kill liveness handling
|
2017-09-14 15:53:11 +00:00 |
|
ifcvt-simple-bprob.ll
|
[IfConversion] Only renormalize probabilities if branches are analyzable
|
2017-03-06 19:12:42 +00:00 |
|
indirect-br.ll
|
…
|
|
|
inline-asm-a.ll
|
[Hexagon] Add inline-asm constraint 'a' for modifier register class
|
2017-07-21 17:51:27 +00:00 |
|
inline-asm-bad-constraint.ll
|
[Hexagon] Report error instead of crashing on wrong inline-asm constraints
|
2017-10-20 20:24:44 +00:00 |
|
inline-asm-hexagon.ll
|
[Hexagon] Add support for proper handling of H and L constraints
|
2016-07-26 17:31:02 +00:00 |
|
inline-asm-i1.ll
|
[Hexagon] Add RUN line to test
|
2016-08-19 19:36:35 +00:00 |
|
inline-asm-qv.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
inline-asm-vecpred128.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
insert-basic.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
insert4.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
invalid-dotnew-attempt.mir
|
[Hexagon] Fix dependence check in the packetizer
|
2017-06-01 18:02:40 +00:00 |
|
is-legal-void.ll
|
[Hexagon] Do not check alignment for unsized types in isLegalAddressingMode
|
2016-08-03 15:06:18 +00:00 |
|
isel-combine-half.ll
|
[Hexagon] Add patterns to select A2_combine_ll and its variants
|
2017-11-22 20:55:41 +00:00 |
|
isel-exti1.ll
|
[Hexagon] Fix instruction selection for sign-extending i1 to i64
|
2017-02-28 22:37:01 +00:00 |
|
isel-global-offset-alignment.ll
|
Revert: [Hexagon] Make sure that offset on globals matches alignment requirements
|
2018-01-30 18:10:27 +00:00 |
|
isel-i1arg-crash.ll
|
[Hexagon] Fix lowering of formal arguments of type i1
|
2017-03-01 17:30:10 +00:00 |
|
isel-op-zext-i1.ll
|
[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
|
2017-03-09 16:29:30 +00:00 |
|
isel-prefer.ll
|
[Hexagon] Add patterns to select A2_combine_ll and its variants
|
2017-11-22 20:55:41 +00:00 |
|
isel-simplify-crash.ll
|
[Hexagon] Run late copy propagation and dead code elimination passes
|
2018-01-24 17:48:11 +00:00 |
|
jt-in-text.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
lit.local.cfg
|
…
|
|
|
livephysregs-add-pristines.mir
|
[IfConversion] More simple, correct dead/kill liveness handling
|
2017-09-14 15:53:11 +00:00 |
|
livephysregs-lane-masks.mir
|
[Hexagon] Add support for Hexagon V65
|
2017-12-11 18:57:54 +00:00 |
|
livephysregs-lane-masks2.mir
|
Insert IMPLICIT_DEFS for undef uses in tail merging
|
2017-09-06 20:45:24 +00:00 |
|
loadi1-G0.ll
|
…
|
|
|
loadi1-v4-G0.ll
|
…
|
|
|
loadi1-v4.ll
|
…
|
|
|
loadi1.ll
|
…
|
|
|
long-calls.ll
|
[Hexagon] Add target feature to generate long calls
|
2016-07-25 14:42:11 +00:00 |
|
loop-prefetch.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
lower-extract-subvector.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
macint.ll
|
…
|
|
|
maxd.ll
|
…
|
|
|
maxh.ll
|
…
|
|
|
maxud.ll
|
…
|
|
|
maxuw.ll
|
…
|
|
|
maxw.ll
|
…
|
|
|
mem-fi-add.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
memcpy-likely-aligned.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
memops-stack.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
memops.ll
|
[Hexagon] Improve patterns with stack-based addressing
|
2016-07-15 15:35:52 +00:00 |
|
memops1.ll
|
…
|
|
|
memops2.ll
|
…
|
|
|
memops3.ll
|
…
|
|
|
mind.ll
|
…
|
|
|
minu-zext-8.ll
|
…
|
|
|
minu-zext-16.ll
|
…
|
|
|
minud.ll
|
…
|
|
|
minuw.ll
|
…
|
|
|
minw.ll
|
…
|
|
|
misaligned-access.ll
|
…
|
|
|
misaligned_double_vector_store_not_fast.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
misched-top-rptracker-sync.ll
|
Reset the TopRPTracker's position in ScheduleDAGMILive::initQueues
|
2016-04-28 19:17:44 +00:00 |
|
mpy.ll
|
…
|
|
|
mul64-sext.ll
|
[Hexagon] Improve code generation for 32x32-bit multiplication
|
2017-05-30 17:47:51 +00:00 |
|
mulh.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
mulhs.ll
|
[Hexagon] Add pattern for 64-bit mulhs
|
2016-08-08 19:24:25 +00:00 |
|
multi-cycle.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
mux-basic.ll
|
…
|
|
|
mux-kill1.mir
|
[Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux
|
2017-06-22 20:43:02 +00:00 |
|
mux-kill2.mir
|
[Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux
|
2017-06-22 20:43:02 +00:00 |
|
mux-kill3.mir
|
[Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux
|
2017-06-22 20:43:02 +00:00 |
|
mux-undef.ll
|
[Hexagon] Skip mux generation when predicate register is undefined
|
2017-06-08 20:56:36 +00:00 |
|
newify-crash.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
newvalueSameReg.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
newvaluejump-c4.mir
|
[Hexagon] Recognize C4_cmpneqi, C4_cmpltei and C4_cmplteui in NewValueJump
|
2017-07-24 19:35:48 +00:00 |
|
newvaluejump-kill.ll
|
[Hexagon] Run late copy propagation and dead code elimination passes
|
2018-01-24 17:48:11 +00:00 |
|
newvaluejump-kill2.mir
|
[Hexagon] Update kills in hexagon-nvj even more properly than before
|
2017-06-27 18:37:16 +00:00 |
|
newvaluejump-solo.mir
|
[Hexagon] Fix wrong check in test/CodeGen/Hexagon/newvaluejump-solo.mir
|
2017-11-30 21:23:19 +00:00 |
|
newvaluejump.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
newvaluejump2.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
newvaluejump3.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
newvaluestore.ll
|
[Hexagon] Enable the post-RA scheduler
|
2016-05-26 19:44:28 +00:00 |
|
opt-addr-mode.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
opt-fabs.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
opt-fneg.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
opt-spill-volatile.ll
|
Add address space mangling to lifetime intrinsics
|
2017-04-10 20:18:21 +00:00 |
|
packetize-cfi-location.ll
|
[Hexagon] Insert CFI instructions before throwing calls
|
2016-07-28 19:13:46 +00:00 |
|
packetize-load-store-aliasing.mir
|
[Packetizer] Add function to check for aliasing between instructions
|
2017-10-20 22:08:40 +00:00 |
|
packetize-nvj-no-prune.mir
|
[Hexagon] Make sure that new-value jump is packetized with producer
|
2017-10-11 21:20:43 +00:00 |
|
packetize-return-arg.ll
|
[Hexagon] Packetize return value setup with the return instruction
|
2016-08-23 16:01:01 +00:00 |
|
packetize-tailcall-arg.ll
|
[Hexagon] Packetize function call arguments with tail call instructions
|
2016-07-14 19:30:55 +00:00 |
|
packetize_cond_inst.ll
|
…
|
|
|
peephole-kill-flags.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
peephole-op-swap.ll
|
[Hexagon] Fix operand swapping in HexagonPeephole
|
2016-04-19 21:36:24 +00:00 |
|
pic-jumptables.ll
|
[Hexagon] Add PIC support
|
2015-12-18 20:19:30 +00:00 |
|
pic-local.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
pic-regusage.ll
|
[Hexagon] Generate PIC-specific versions of save/restore routines
|
2016-03-24 19:18:48 +00:00 |
|
pic-simple.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
pic-static.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
plt-rel.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
post-inc-aa-metadata.ll
|
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
|
2017-12-07 10:40:31 +00:00 |
|
post-ra-kill-update.mir
|
ScheduleDAGInstrs: Fix fixupKills()
|
2017-05-27 02:50:50 +00:00 |
|
postinc-baseoffset.mir
|
[Hexagon] Fix a bug in r308502: post-inc offset is always 0
|
2017-07-19 19:17:32 +00:00 |
|
postinc-load.ll
|
…
|
|
|
postinc-offset.ll
|
[Hexagon] Implement RDF-based post-RA optimizations
|
2016-01-12 19:09:01 +00:00 |
|
postinc-store.ll
|
…
|
|
|
pred-absolute-store.ll
|
[RDF] Remove the map of reaching defs from copy propagation
|
2017-03-10 22:44:24 +00:00 |
|
pred-gp.ll
|
…
|
|
|
pred-instrs.ll
|
…
|
|
|
predicate-copy.ll
|
…
|
|
|
predicate-logical.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
predicate-rcmp.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
propagate-vcombine.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
rdf-copy-renamable-reserved.mir
|
[RDF] Clear the renamable flag when copy propagating reserved registers
|
2018-01-30 23:19:44 +00:00 |
|
rdf-copy-undef2.ll
|
Add address space mangling to lifetime intrinsics
|
2017-04-10 20:18:21 +00:00 |
|
rdf-copy.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
rdf-cover-use.ll
|
[RDF] Remove covered parts of reached uses for phi and use in same block
|
2017-05-05 22:10:32 +00:00 |
|
rdf-dead-loop.ll
|
[Hexagon] Implement RDF-based post-RA optimizations
|
2016-01-12 19:09:01 +00:00 |
|
rdf-def-mask.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
rdf-ehlabel-live.mir
|
[Hexagon] Make sure that RDF does not remove EH_LABELs
|
2017-11-21 21:05:51 +00:00 |
|
rdf-extra-livein.ll
|
[RDF] Fix liveness propagation through shadows
|
2016-10-03 20:17:20 +00:00 |
|
rdf-filter-defs.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
rdf-ignore-undef.ll
|
[RDF] Ignore undef use operands
|
2016-09-06 17:03:13 +00:00 |
|
rdf-inline-asm-fixed.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
rdf-inline-asm.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
rdf-multiple-phis-up.ll
|
[RDF] Further improve handling of multiple phis reached from shadows
|
2016-09-08 20:48:42 +00:00 |
|
rdf-phi-shadows.ll
|
[RDF] Fix liveness analysis for phi nodes with shadow uses
|
2016-09-07 20:37:05 +00:00 |
|
rdf-phi-up.ll
|
Add address space mangling to lifetime intrinsics
|
2017-04-10 20:18:21 +00:00 |
|
rdf-reset-kills.ll
|
[RDF] Consider register as live if any alias is live
|
2016-04-20 14:33:23 +00:00 |
|
readcyclecounter.ll
|
[Hexagon] Implement @llvm.readcyclecounter()
|
2017-02-22 22:28:47 +00:00 |
|
reg-scavengebug-3.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
reg-scavenger-valid-slot.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
regalloc-bad-undef.mir
|
[MachineOperand][MIR] Add isRenamable to MachineOperand.
|
2017-12-12 17:53:59 +00:00 |
|
regalloc-block-overlap.ll
|
[Hexagon] Run late copy propagation and dead code elimination passes
|
2018-01-24 17:48:11 +00:00 |
|
regalloc-liveout-undef.mir
|
MIR: Print the register class or bank in vreg defs
|
2017-10-24 18:04:54 +00:00 |
|
relax.ll
|
Revert r265817
|
2016-04-08 18:15:37 +00:00 |
|
remove-endloop.ll
|
…
|
|
|
remove_lsr.ll
|
…
|
|
|
restore-single-reg.ll
|
[Hexagon] Only use restore functions for single register at -Oz
|
2016-03-28 14:52:21 +00:00 |
|
ret-struct-by-val.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
runtime-stkchk.ll
|
Add address space mangling to lifetime intrinsics
|
2017-04-10 20:18:21 +00:00 |
|
sdata-array.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
sdata-basic.ll
|
[Hexagon] Expand handling of the small-data/bss section
|
2016-04-21 18:56:45 +00:00 |
|
sdr-basic.ll
|
[Hexagon] Split double registers
|
2015-10-16 20:38:54 +00:00 |
|
sdr-shr32.ll
|
[Hexagon] Split double registers
|
2015-10-16 20:38:54 +00:00 |
|
section_7275.ll
|
[Hexagon] Adding gp+ to the syntax of gp-relative instructions
|
2017-02-06 23:18:57 +00:00 |
|
select-instr-align.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
sf-min-max.ll
|
[Hexagon] Add extra patterns for single-precision min/max instructions
|
2016-08-10 17:56:24 +00:00 |
|
sffms.ll
|
[Hexagon] Improvements to handling and generation of FP instructions
|
2016-08-19 13:34:31 +00:00 |
|
shrink-frame-basic.ll
|
…
|
|
|
signed_immediates.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
simple_addend.ll
|
[Hexagon] Delay emission of CFI instructions
|
2015-10-19 17:46:01 +00:00 |
|
simpletailcall.ll
|
…
|
|
|
split-const32-const64.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
stack-align-reset.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
stack-align1.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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stack-align2.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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stack-alloca1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
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stack-alloca2.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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static.ll
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[Hexagon] Adding gp+ to the syntax of gp-relative instructions
|
2017-02-06 23:18:57 +00:00 |
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store-imm-amode.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
store-imm-large-stack.ll
|
[Hexagon] Recognize potential offset overflow for store-imm to stack
|
2017-06-22 14:11:23 +00:00 |
|
store-imm-stack-object.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
store-shift.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
store-widen-aliased-load.ll
|
…
|
|
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store-widen-negv.ll
|
…
|
|
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store-widen-negv2.ll
|
…
|
|
|
store-widen.ll
|
…
|
|
|
storerd-io-over-rr.ll
|
[Hexagon] Prefer _io over _rr for 64-bit store with constant offset
|
2016-08-02 18:50:05 +00:00 |
|
storerinewabs.ll
|
[Hexagon] Fix printing the address operand of S2_storerinewabs
|
2016-04-19 20:20:33 +00:00 |
|
struct_args.ll
|
[Hexagon] Bitwise operations for insert/extract word not simplified
|
2016-07-26 18:30:11 +00:00 |
|
struct_args_large.ll
|
The canonical way to XFAIL a test for all targets is XFAIL: *, not XFAIL:
|
2016-02-04 16:21:38 +00:00 |
|
sube.ll
|
[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
|
2017-03-09 16:29:30 +00:00 |
|
subi-asl.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
switch-lut-explicit-section.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
switch-lut-function-section.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
switch-lut-multiple-functions.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
switch-lut-text-section.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
swp-const-tc.ll
|
[LSR / TTI / SystemZ] Eliminate TargetTransformInfo::isFoldableMemAccess()
|
2017-08-09 11:28:01 +00:00 |
|
swp-dag-phi.ll
|
MachinePipeliner pass that implements Swing Modulo Scheduling
|
2016-07-29 16:44:44 +00:00 |
|
swp-epilog-phi10.ll
|
Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
|
2016-12-22 18:49:55 +00:00 |
|
swp-epilog-reuse-1.ll
|
[NFC] fix trivial typos in comments
|
2018-01-24 05:04:35 +00:00 |
|
swp-epilog-reuse.ll
|
MachinePipeliner pass that implements Swing Modulo Scheduling
|
2016-07-29 16:44:44 +00:00 |
|
swp-matmul-bitext.ll
|
[Hexagon] Use automatically-generated scheduling information for HVX
|
2017-05-03 20:10:36 +00:00 |
|
swp-max.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
swp-multi-loops.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
swp-order-copies.ll
|
[Pipeliner] Improve serialization order for post-increments
|
2017-10-11 15:51:44 +00:00 |
|
swp-prolog-phi4.ll
|
Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
|
2016-12-22 18:49:55 +00:00 |
|
swp-stages4.ll
|
[Hexagon] Adjust patterns to reflect instruction selection preferences
|
2017-10-27 22:24:49 +00:00 |
|
swp-stages5.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
swp-vect-dotprod.ll
|
MachinePipeliner pass that implements Swing Modulo Scheduling
|
2016-07-29 16:44:44 +00:00 |
|
swp-vmult.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
swp-vsum.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
tail-call-mem-intrinsics.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
tail-call-trunc.ll
|
…
|
|
|
tail-dup-subreg-abort.ll
|
Tail duplication can mix incompatible registers in phi nodes
|
2015-10-21 02:40:06 +00:00 |
|
tail-dup-subreg-map.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
tailcall_fastcc_ccc.ll
|
[Hexagon] Allow tail-call optimization when mixing C and fast calling conv
|
2016-08-19 15:02:18 +00:00 |
|
target-flag-ext.mir
|
[Hexagon] Fix check for HMOTF_ConstExtend operand flag
|
2017-07-10 18:38:52 +00:00 |
|
tfr-to-combine.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
tls_pic.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
tls_static.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
trap-unreachable.ll
|
[Hexagon] Add option to generate calls to "abort" for "unreachable"
|
2017-09-06 16:22:55 +00:00 |
|
two-crash.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
undo-dag-shift.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
union-1.ll
|
[Hexagon] Split double registers
|
2015-10-16 20:38:54 +00:00 |
|
unreachable-mbb-phi-subreg.mir
|
MIR: Print the register class or bank in vreg defs
|
2017-10-24 18:04:54 +00:00 |
|
usr-ovf-dep.ll
|
…
|
|
|
v6vec-vprint.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
v60-cur.ll
|
[Hexagon] Allow construction of HVX vector predicates
|
2017-12-20 20:49:43 +00:00 |
|
v60-vsel1.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
v60Intrins.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
v60Vasr.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
v60small.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vaddh.ll
|
[Hexagon] Replace instruction definitions with auto-generated ones
|
2017-02-10 15:33:13 +00:00 |
|
validate-offset.ll
|
…
|
|
|
vassign-to-combine.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vdmpy-halide-test.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vec-pred-spill1.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vec-vararg-align.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vector-align.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vector-ext-load.ll
|
[Hexagon] Expand sext- and zextloads of vector types, not just extloads
|
2016-09-08 17:42:14 +00:00 |
|
vextract-basic.mir
|
[Hexagon] Replace multiple vector extracts with store-load combinations
|
2018-01-26 21:17:14 +00:00 |
|
vload-postinc-sel.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vmpa-halide-test.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vpack_eo.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vselect-pseudo.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vsplat-isel.ll
|
[Hexagon] Properly handle instruction selection of vsplat intrinsics
|
2016-05-12 17:21:40 +00:00 |
|
zextloadi1.ll
|
[Hexagon] Minimize number of repeated constant extenders
|
2017-10-13 19:02:59 +00:00 |
1108ee2496