llvm-project/llvm/test/CodeGen
Matt Arsenault b46c191c49 AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnum
Patch by Tom Stellard

llvm-svn: 326567
2018-03-02 12:23:00 +00:00
..
AArch64 [DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors. 2018-03-01 22:32:25 +00:00
AMDGPU AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnum 2018-03-02 12:23:00 +00:00
ARC
ARM [TLS] use emulated TLS if the target supports only this mode 2018-02-28 17:48:55 +00:00
AVR [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
BPF bpf: New codegen testcases for 32-bit subregister support 2018-02-23 23:49:33 +00:00
Generic [DebugInfo] Add remaining files to r325970 2018-02-23 23:13:18 +00:00
Hexagon [Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiply 2018-02-27 22:44:41 +00:00
Inputs
Lanai Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
MIR [MIRParser] Accept overloaded intrinsic names w/o type suffixes 2018-02-28 23:51:49 +00:00
MSP430 Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
Mips [TLS] use emulated TLS if the target supports only this mode 2018-02-28 17:48:55 +00:00
NVPTX [DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors. 2018-03-01 22:32:25 +00:00
Nios2
PowerPC [DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors. 2018-03-01 22:32:25 +00:00
RISCV [RISCV] Update two tests after r326208 2018-02-28 08:20:47 +00:00
SPARC Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
SystemZ [DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors. 2018-03-01 22:32:25 +00:00
Thumb Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
Thumb2 ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR. 2018-02-27 19:00:59 +00:00
WebAssembly [WebAssembly] Add mechanisms for specifying an explicit import module name. 2018-02-09 23:13:22 +00:00
WinCFGuard
WinEH
X86 [DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors. 2018-03-01 22:32:25 +00:00
XCore [XCore] Return true in enableMultipleCopyHints(). 2018-02-26 08:03:32 +00:00