forked from OSchip/llvm-project
832 lines
25 KiB
C++
832 lines
25 KiB
C++
//===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsInstrInfo.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "MipsGenInstrInfo.inc"
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// Pin the vtable to this file.
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void MipsInstrInfo::anchor() {}
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MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
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: MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
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Subtarget(STI), UncondBrOpc(UncondBr) {}
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const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
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if (STI.inMips16Mode())
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return createMips16InstrInfo(STI);
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return createMipsSEInstrInfo(STI);
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}
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bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
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return op.isImm() && op.getImm() == 0;
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}
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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// FIXME: This appears to be dead code.
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void MipsInstrInfo::
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
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{
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DebugLoc DL;
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BuildMI(MBB, MI, DL, get(Mips::NOP));
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}
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MachineMemOperand *
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MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
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MachineMemOperand::Flags Flags) const {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
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Flags, MFI.getObjectSize(FI), Align);
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
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MachineBasicBlock *&BB,
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
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int NumOp = Inst->getNumExplicitOperands();
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// for both int and fp branches, the last explicit operand is the
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// MBB.
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BB = Inst->getOperand(NumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(Opc));
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for (int i = 0; i < NumOp-1; i++)
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Cond.push_back(Inst->getOperand(i));
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}
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bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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SmallVector<MachineInstr*, 2> BranchInstrs;
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BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
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return (BT == BT_None) || (BT == BT_Indirect);
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}
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void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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const DebugLoc &DL,
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ArrayRef<MachineOperand> Cond) const {
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unsigned Opc = Cond[0].getImm();
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const MCInstrDesc &MCID = get(Opc);
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MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
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for (unsigned i = 1; i < Cond.size(); ++i) {
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assert((Cond[i].isImm() || Cond[i].isReg()) &&
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"Cannot copy operand for conditional branch!");
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MIB.add(Cond[i]);
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}
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MIB.addMBB(TBB);
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}
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unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded) const {
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// Shouldn't be a fall through.
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assert(TBB && "insertBranch must not be told to insert a fallthrough");
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assert(!BytesAdded && "code size not handled");
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// # of condition operands:
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// Unconditional branches: 0
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// Floating point branches: 1 (opc)
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// Int BranchZero: 2 (opc, reg)
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// Int Branch: 3 (opc, reg0, reg1)
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assert((Cond.size() <= 3) &&
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"# of Mips branch conditions must be <= 3!");
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// Two-way Conditional branch.
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if (FBB) {
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BuildCondBr(MBB, TBB, DL, Cond);
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BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
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return 2;
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}
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// One way branch.
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// Unconditional branch.
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if (Cond.empty())
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BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
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else // Conditional branch.
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BuildCondBr(MBB, TBB, DL, Cond);
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return 1;
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}
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unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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assert(!BytesRemoved && "code size not handled");
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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unsigned removed = 0;
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// Up to 2 branches are removed.
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// Note that indirect branches are not removed.
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while (I != REnd && removed < 2) {
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// Skip past debug instructions.
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if (I->isDebugInstr()) {
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++I;
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continue;
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}
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if (!getAnalyzableBrOpc(I->getOpcode()))
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break;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.rbegin();
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++removed;
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}
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return removed;
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}
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/// reverseBranchCondition - Return the inverse opcode of the
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/// specified Branch instruction.
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bool MipsInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert( (Cond.size() && Cond.size() <= 3) &&
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"Invalid Mips branch condition!");
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Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
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return false;
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}
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MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
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SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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// Skip all the debug instructions.
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while (I != REnd && I->isDebugInstr())
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++I;
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if (I == REnd || !isUnpredicatedTerminator(*I)) {
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// This block ends with no branches (it just falls through to its succ).
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// Leave TBB/FBB null.
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TBB = FBB = nullptr;
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return BT_NoBranch;
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}
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MachineInstr *LastInst = &*I;
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unsigned LastOpc = LastInst->getOpcode();
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BranchInstrs.push_back(LastInst);
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// Not an analyzable branch (e.g., indirect jump).
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if (!getAnalyzableBrOpc(LastOpc))
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return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
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// Get the second to last instruction in the block.
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unsigned SecondLastOpc = 0;
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MachineInstr *SecondLastInst = nullptr;
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// Skip past any debug instruction to see if the second last actual
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// is a branch.
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++I;
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while (I != REnd && I->isDebugInstr())
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++I;
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if (I != REnd) {
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SecondLastInst = &*I;
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SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
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// Not an analyzable branch (must be an indirect jump).
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if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
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return BT_None;
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}
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// If there is only one terminator instruction, process it.
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if (!SecondLastOpc) {
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// Unconditional branch.
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if (LastInst->isUnconditionalBranch()) {
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TBB = LastInst->getOperand(0).getMBB();
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return BT_Uncond;
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}
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// Conditional branch
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AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
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return BT_Cond;
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}
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// If we reached here, there are two branches.
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// If there are three terminators, we don't know what sort of block this is.
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if (++I != REnd && isUnpredicatedTerminator(*I))
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return BT_None;
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BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
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// If second to last instruction is an unconditional branch,
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// analyze it and remove the last instruction.
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if (SecondLastInst->isUnconditionalBranch()) {
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// Return if the last instruction cannot be removed.
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if (!AllowModify)
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return BT_None;
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TBB = SecondLastInst->getOperand(0).getMBB();
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LastInst->eraseFromParent();
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BranchInstrs.pop_back();
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return BT_Uncond;
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}
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// Conditional branch followed by an unconditional branch.
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// The last one must be unconditional.
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if (!LastInst->isUnconditionalBranch())
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return BT_None;
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AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
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FBB = LastInst->getOperand(0).getMBB();
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return BT_CondUncond;
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}
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bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {
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switch (BranchOpc) {
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case Mips::B:
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case Mips::BAL:
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case Mips::BAL_BR:
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case Mips::BAL_BR_MM:
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case Mips::BC1F:
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case Mips::BC1FL:
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case Mips::BC1T:
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case Mips::BC1TL:
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case Mips::BEQ: case Mips::BEQ64:
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case Mips::BEQL:
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case Mips::BGEZ: case Mips::BGEZ64:
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case Mips::BGEZL:
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case Mips::BGEZAL:
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case Mips::BGEZALL:
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case Mips::BGTZ: case Mips::BGTZ64:
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case Mips::BGTZL:
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case Mips::BLEZ: case Mips::BLEZ64:
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case Mips::BLEZL:
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case Mips::BLTZ: case Mips::BLTZ64:
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case Mips::BLTZL:
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case Mips::BLTZAL:
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case Mips::BLTZALL:
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case Mips::BNE: case Mips::BNE64:
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case Mips::BNEL:
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return isInt<18>(BrOffset);
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// microMIPSr3 branches
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case Mips::B_MM:
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case Mips::BC1F_MM:
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case Mips::BC1T_MM:
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case Mips::BEQ_MM:
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case Mips::BGEZ_MM:
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case Mips::BGEZAL_MM:
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case Mips::BGTZ_MM:
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case Mips::BLEZ_MM:
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case Mips::BLTZ_MM:
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case Mips::BLTZAL_MM:
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case Mips::BNE_MM:
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case Mips::BEQZC_MM:
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case Mips::BNEZC_MM:
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return isInt<17>(BrOffset);
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// microMIPSR3 short branches.
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case Mips::B16_MM:
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return isInt<11>(BrOffset);
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case Mips::BEQZ16_MM:
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case Mips::BNEZ16_MM:
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return isInt<8>(BrOffset);
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// MIPSR6 branches.
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case Mips::BALC:
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case Mips::BC:
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return isInt<28>(BrOffset);
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case Mips::BC1EQZ:
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case Mips::BC1NEZ:
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case Mips::BC2EQZ:
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case Mips::BC2NEZ:
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case Mips::BEQC: case Mips::BEQC64:
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case Mips::BNEC: case Mips::BNEC64:
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case Mips::BGEC: case Mips::BGEC64:
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case Mips::BGEUC: case Mips::BGEUC64:
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case Mips::BGEZC: case Mips::BGEZC64:
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case Mips::BGTZC: case Mips::BGTZC64:
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case Mips::BLEZC: case Mips::BLEZC64:
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case Mips::BLTC: case Mips::BLTC64:
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case Mips::BLTUC: case Mips::BLTUC64:
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case Mips::BLTZC: case Mips::BLTZC64:
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case Mips::BNVC:
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case Mips::BOVC:
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case Mips::BGEZALC:
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case Mips::BEQZALC:
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case Mips::BGTZALC:
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case Mips::BLEZALC:
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case Mips::BLTZALC:
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case Mips::BNEZALC:
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return isInt<18>(BrOffset);
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case Mips::BEQZC: case Mips::BEQZC64:
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case Mips::BNEZC: case Mips::BNEZC64:
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return isInt<23>(BrOffset);
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// microMIPSR6 branches
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case Mips::BC16_MMR6:
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return isInt<11>(BrOffset);
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case Mips::BEQZC16_MMR6:
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case Mips::BNEZC16_MMR6:
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return isInt<8>(BrOffset);
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case Mips::BALC_MMR6:
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case Mips::BC_MMR6:
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return isInt<27>(BrOffset);
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case Mips::BC1EQZC_MMR6:
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case Mips::BC1NEZC_MMR6:
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case Mips::BC2EQZC_MMR6:
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case Mips::BC2NEZC_MMR6:
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case Mips::BGEZALC_MMR6:
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case Mips::BEQZALC_MMR6:
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case Mips::BGTZALC_MMR6:
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case Mips::BLEZALC_MMR6:
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case Mips::BLTZALC_MMR6:
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case Mips::BNEZALC_MMR6:
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case Mips::BNVC_MMR6:
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case Mips::BOVC_MMR6:
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return isInt<17>(BrOffset);
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case Mips::BEQC_MMR6:
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case Mips::BNEC_MMR6:
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case Mips::BGEC_MMR6:
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case Mips::BGEUC_MMR6:
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case Mips::BGEZC_MMR6:
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case Mips::BGTZC_MMR6:
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case Mips::BLEZC_MMR6:
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case Mips::BLTC_MMR6:
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case Mips::BLTUC_MMR6:
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case Mips::BLTZC_MMR6:
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return isInt<18>(BrOffset);
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case Mips::BEQZC_MMR6:
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case Mips::BNEZC_MMR6:
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return isInt<23>(BrOffset);
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// DSP branches.
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case Mips::BPOSGE32:
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return isInt<18>(BrOffset);
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case Mips::BPOSGE32_MM:
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case Mips::BPOSGE32C_MMR3:
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return isInt<17>(BrOffset);
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// cnMIPS branches.
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case Mips::BBIT0:
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case Mips::BBIT032:
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case Mips::BBIT1:
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case Mips::BBIT132:
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return isInt<18>(BrOffset);
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// MSA branches.
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case Mips::BZ_B:
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case Mips::BZ_H:
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case Mips::BZ_W:
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case Mips::BZ_D:
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case Mips::BZ_V:
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case Mips::BNZ_B:
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case Mips::BNZ_H:
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case Mips::BNZ_W:
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case Mips::BNZ_D:
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case Mips::BNZ_V:
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return isInt<18>(BrOffset);
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}
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llvm_unreachable("Unknown branch instruction!");
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}
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/// Return the corresponding compact (no delay slot) form of a branch.
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unsigned MipsInstrInfo::getEquivalentCompactForm(
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const MachineBasicBlock::iterator I) const {
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unsigned Opcode = I->getOpcode();
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bool canUseShortMicroMipsCTI = false;
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if (Subtarget.inMicroMipsMode()) {
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switch (Opcode) {
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case Mips::BNE:
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case Mips::BNE_MM:
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case Mips::BEQ:
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case Mips::BEQ_MM:
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// microMIPS has NE,EQ branches that do not have delay slots provided one
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// of the operands is zero.
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if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
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canUseShortMicroMipsCTI = true;
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break;
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// For microMIPS the PseudoReturn and PseudoIndirectBranch are always
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// expanded to JR_MM, so they can be replaced with JRC16_MM.
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case Mips::JR:
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case Mips::PseudoReturn:
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case Mips::PseudoIndirectBranch:
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canUseShortMicroMipsCTI = true;
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break;
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}
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}
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// MIPSR6 forbids both operands being the zero register.
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if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
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(I->getOperand(0).isReg() &&
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(I->getOperand(0).getReg() == Mips::ZERO ||
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I->getOperand(0).getReg() == Mips::ZERO_64)) &&
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(I->getOperand(1).isReg() &&
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(I->getOperand(1).getReg() == Mips::ZERO ||
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I->getOperand(1).getReg() == Mips::ZERO_64)))
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return 0;
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if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
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switch (Opcode) {
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case Mips::B:
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return Mips::BC;
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case Mips::BAL:
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return Mips::BALC;
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case Mips::BEQ:
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case Mips::BEQ_MM:
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if (canUseShortMicroMipsCTI)
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return Mips::BEQZC_MM;
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else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
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return 0;
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return Mips::BEQC;
|
|
case Mips::BNE:
|
|
case Mips::BNE_MM:
|
|
if (canUseShortMicroMipsCTI)
|
|
return Mips::BNEZC_MM;
|
|
else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
|
|
return 0;
|
|
return Mips::BNEC;
|
|
case Mips::BGE:
|
|
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
|
|
return 0;
|
|
return Mips::BGEC;
|
|
case Mips::BGEU:
|
|
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
|
|
return 0;
|
|
return Mips::BGEUC;
|
|
case Mips::BGEZ:
|
|
return Mips::BGEZC;
|
|
case Mips::BGTZ:
|
|
return Mips::BGTZC;
|
|
case Mips::BLEZ:
|
|
return Mips::BLEZC;
|
|
case Mips::BLT:
|
|
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
|
|
return 0;
|
|
return Mips::BLTC;
|
|
case Mips::BLTU:
|
|
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
|
|
return 0;
|
|
return Mips::BLTUC;
|
|
case Mips::BLTZ:
|
|
return Mips::BLTZC;
|
|
case Mips::BEQ64:
|
|
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
|
|
return 0;
|
|
return Mips::BEQC64;
|
|
case Mips::BNE64:
|
|
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
|
|
return 0;
|
|
return Mips::BNEC64;
|
|
case Mips::BGTZ64:
|
|
return Mips::BGTZC64;
|
|
case Mips::BGEZ64:
|
|
return Mips::BGEZC64;
|
|
case Mips::BLTZ64:
|
|
return Mips::BLTZC64;
|
|
case Mips::BLEZ64:
|
|
return Mips::BLEZC64;
|
|
// For MIPSR6, the instruction 'jic' can be used for these cases. Some
|
|
// tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
|
|
case Mips::JR:
|
|
case Mips::PseudoIndirectBranchR6:
|
|
case Mips::PseudoReturn:
|
|
case Mips::TAILCALLR6REG:
|
|
if (canUseShortMicroMipsCTI)
|
|
return Mips::JRC16_MM;
|
|
return Mips::JIC;
|
|
case Mips::JALRPseudo:
|
|
return Mips::JIALC;
|
|
case Mips::JR64:
|
|
case Mips::PseudoIndirectBranch64R6:
|
|
case Mips::PseudoReturn64:
|
|
case Mips::TAILCALL64R6REG:
|
|
return Mips::JIC64;
|
|
case Mips::JALR64Pseudo:
|
|
return Mips::JIALC64;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/// Predicate for distingushing between control transfer instructions and all
|
|
/// other instructions for handling forbidden slots. Consider inline assembly
|
|
/// as unsafe as well.
|
|
bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
|
|
if (MI.isInlineAsm())
|
|
return false;
|
|
|
|
return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
|
|
}
|
|
|
|
/// Predicate for distingushing instructions that have forbidden slots.
|
|
bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
|
|
return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
|
|
}
|
|
|
|
/// Return the number of bytes of code the specified instruction may be.
|
|
unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
return MI.getDesc().getSize();
|
|
case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
|
|
const MachineFunction *MF = MI.getParent()->getParent();
|
|
const char *AsmStr = MI.getOperand(0).getSymbolName();
|
|
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
|
|
}
|
|
case Mips::CONSTPOOL_ENTRY:
|
|
// If this machine instr is a constant pool entry, its size is recorded as
|
|
// operand #2.
|
|
return MI.getOperand(2).getImm();
|
|
}
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
|
|
MachineBasicBlock::iterator I) const {
|
|
MachineInstrBuilder MIB;
|
|
|
|
// Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
|
|
// Pick the zero form of the branch for readable assembly and for greater
|
|
// branch distance in non-microMIPS mode.
|
|
// Additional MIPSR6 does not permit the use of register $zero for compact
|
|
// branches.
|
|
// FIXME: Certain atomic sequences on mips64 generate 32bit references to
|
|
// Mips::ZERO, which is incorrect. This test should be updated to use
|
|
// Subtarget.getABI().GetZeroReg() when those atomic sequences and others
|
|
// are fixed.
|
|
int ZeroOperandPosition = -1;
|
|
bool BranchWithZeroOperand = false;
|
|
if (I->isBranch() && !I->isPseudo()) {
|
|
auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
|
|
ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
|
|
BranchWithZeroOperand = ZeroOperandPosition != -1;
|
|
}
|
|
|
|
if (BranchWithZeroOperand) {
|
|
switch (NewOpc) {
|
|
case Mips::BEQC:
|
|
NewOpc = Mips::BEQZC;
|
|
break;
|
|
case Mips::BNEC:
|
|
NewOpc = Mips::BNEZC;
|
|
break;
|
|
case Mips::BGEC:
|
|
NewOpc = Mips::BGEZC;
|
|
break;
|
|
case Mips::BLTC:
|
|
NewOpc = Mips::BLTZC;
|
|
break;
|
|
case Mips::BEQC64:
|
|
NewOpc = Mips::BEQZC64;
|
|
break;
|
|
case Mips::BNEC64:
|
|
NewOpc = Mips::BNEZC64;
|
|
break;
|
|
}
|
|
}
|
|
|
|
MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
|
|
|
|
// For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
|
|
// immediate 0 as an operand and requires the removal of it's implicit-def %ra
|
|
// implicit operand as copying the implicit operations of the instructio we're
|
|
// looking at will give us the correct flags.
|
|
if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
|
|
NewOpc == Mips::JIALC64) {
|
|
|
|
if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
|
|
MIB->RemoveOperand(0);
|
|
|
|
for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
|
|
MIB.add(I->getOperand(J));
|
|
}
|
|
|
|
MIB.addImm(0);
|
|
|
|
} else {
|
|
for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
|
|
if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
|
|
continue;
|
|
|
|
MIB.add(I->getOperand(J));
|
|
}
|
|
}
|
|
|
|
MIB.copyImplicitOps(*I);
|
|
MIB.cloneMemRefs(*I);
|
|
return MIB;
|
|
}
|
|
|
|
bool MipsInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
|
|
unsigned &SrcOpIdx2) const {
|
|
assert(!MI.isBundle() &&
|
|
"TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
|
|
|
|
const MCInstrDesc &MCID = MI.getDesc();
|
|
if (!MCID.isCommutable())
|
|
return false;
|
|
|
|
switch (MI.getOpcode()) {
|
|
case Mips::DPADD_U_H:
|
|
case Mips::DPADD_U_W:
|
|
case Mips::DPADD_U_D:
|
|
case Mips::DPADD_S_H:
|
|
case Mips::DPADD_S_W:
|
|
case Mips::DPADD_S_D:
|
|
// The first operand is both input and output, so it should not commute
|
|
if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
|
|
return false;
|
|
|
|
if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
|
|
return false;
|
|
return true;
|
|
}
|
|
return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
|
|
}
|
|
|
|
// ins, ext, dext*, dins have the following constraints:
|
|
// X <= pos < Y
|
|
// X < size <= Y
|
|
// X < pos+size <= Y
|
|
//
|
|
// dinsm and dinsu have the following constraints:
|
|
// X <= pos < Y
|
|
// X <= size <= Y
|
|
// X < pos+size <= Y
|
|
//
|
|
// The callee of verifyInsExtInstruction however gives the bounds of
|
|
// dins[um] like the other (d)ins (d)ext(um) instructions, so that this
|
|
// function doesn't have to vary it's behaviour based on the instruction
|
|
// being checked.
|
|
static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
|
|
const int64_t PosLow, const int64_t PosHigh,
|
|
const int64_t SizeLow,
|
|
const int64_t SizeHigh,
|
|
const int64_t BothLow,
|
|
const int64_t BothHigh) {
|
|
MachineOperand MOPos = MI.getOperand(2);
|
|
if (!MOPos.isImm()) {
|
|
ErrInfo = "Position is not an immediate!";
|
|
return false;
|
|
}
|
|
int64_t Pos = MOPos.getImm();
|
|
if (!((PosLow <= Pos) && (Pos < PosHigh))) {
|
|
ErrInfo = "Position operand is out of range!";
|
|
return false;
|
|
}
|
|
|
|
MachineOperand MOSize = MI.getOperand(3);
|
|
if (!MOSize.isImm()) {
|
|
ErrInfo = "Size operand is not an immediate!";
|
|
return false;
|
|
}
|
|
int64_t Size = MOSize.getImm();
|
|
if (!((SizeLow < Size) && (Size <= SizeHigh))) {
|
|
ErrInfo = "Size operand is out of range!";
|
|
return false;
|
|
}
|
|
|
|
if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
|
|
ErrInfo = "Position + Size is out of range!";
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
// Perform target specific instruction verification.
|
|
bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
|
|
StringRef &ErrInfo) const {
|
|
// Verify that ins and ext instructions are well formed.
|
|
switch (MI.getOpcode()) {
|
|
case Mips::EXT:
|
|
case Mips::EXT_MM:
|
|
case Mips::INS:
|
|
case Mips::INS_MM:
|
|
case Mips::DINS:
|
|
return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
|
|
case Mips::DINSM:
|
|
// The ISA spec has a subtle difference between dinsm and dextm
|
|
// in that it says:
|
|
// 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
|
|
// To make the bounds checks similar, the range 1 < size <= 64 is checked
|
|
// for 'dinsm'.
|
|
return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
|
|
case Mips::DINSU:
|
|
// The ISA spec has a subtle difference between dinsu and dextu in that
|
|
// the size range of dinsu is specified as 1 <= size <= 32 whereas size
|
|
// for dextu is 0 < size <= 32. The range checked for dinsu here is
|
|
// 0 < size <= 32, which is equivalent and similar to dextu.
|
|
return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
|
|
case Mips::DEXT:
|
|
return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
|
|
case Mips::DEXTM:
|
|
return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
|
|
case Mips::DEXTU:
|
|
return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
|
|
case Mips::TAILCALLREG:
|
|
case Mips::PseudoIndirectBranch:
|
|
case Mips::JR:
|
|
case Mips::JR64:
|
|
case Mips::JALR:
|
|
case Mips::JALR64:
|
|
case Mips::JALRPseudo:
|
|
if (!Subtarget.useIndirectJumpsHazard())
|
|
return true;
|
|
|
|
ErrInfo = "invalid instruction when using jump guards!";
|
|
return false;
|
|
default:
|
|
return true;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
std::pair<unsigned, unsigned>
|
|
MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
|
|
return std::make_pair(TF, 0u);
|
|
}
|
|
|
|
ArrayRef<std::pair<unsigned, const char*>>
|
|
MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
|
|
using namespace MipsII;
|
|
|
|
static const std::pair<unsigned, const char*> Flags[] = {
|
|
{MO_GOT, "mips-got"},
|
|
{MO_GOT_CALL, "mips-got-call"},
|
|
{MO_GPREL, "mips-gprel"},
|
|
{MO_ABS_HI, "mips-abs-hi"},
|
|
{MO_ABS_LO, "mips-abs-lo"},
|
|
{MO_TLSGD, "mips-tlsgd"},
|
|
{MO_TLSLDM, "mips-tlsldm"},
|
|
{MO_DTPREL_HI, "mips-dtprel-hi"},
|
|
{MO_DTPREL_LO, "mips-dtprel-lo"},
|
|
{MO_GOTTPREL, "mips-gottprel"},
|
|
{MO_TPREL_HI, "mips-tprel-hi"},
|
|
{MO_TPREL_LO, "mips-tprel-lo"},
|
|
{MO_GPOFF_HI, "mips-gpoff-hi"},
|
|
{MO_GPOFF_LO, "mips-gpoff-lo"},
|
|
{MO_GOT_DISP, "mips-got-disp"},
|
|
{MO_GOT_PAGE, "mips-got-page"},
|
|
{MO_GOT_OFST, "mips-got-ofst"},
|
|
{MO_HIGHER, "mips-higher"},
|
|
{MO_HIGHEST, "mips-highest"},
|
|
{MO_GOT_HI16, "mips-got-hi16"},
|
|
{MO_GOT_LO16, "mips-got-lo16"},
|
|
{MO_CALL_HI16, "mips-call-hi16"},
|
|
{MO_CALL_LO16, "mips-call-lo16"}
|
|
};
|
|
return makeArrayRef(Flags);
|
|
}
|