forked from OSchip/llvm-project
267 lines
9.7 KiB
LLVM
267 lines
9.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() #0
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declare i32 @llvm.r600.read.tidig.y() #0
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; In this test both the pointer and the offset operands to the
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; BUFFER_LOAD instructions end up being stored in vgprs. This
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; requires us to add the pointer and offset together, store the
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; result in the offset operand (vaddr), and then store 0 in an
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; sgpr register pair and use that for the pointer operand
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; (low 64-bits of srsrc).
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; GCN-LABEL: {{^}}mubuf:
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; Make sure we aren't using VGPRs for the source operand of s_mov_b64
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; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
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; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
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; instructions
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; GCN: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
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; GCN: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
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define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #1 {
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entry:
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%tmp = call i32 @llvm.r600.read.tidig.x()
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%tmp1 = call i32 @llvm.r600.read.tidig.y()
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%tmp2 = sext i32 %tmp to i64
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%tmp3 = sext i32 %tmp1 to i64
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br label %loop
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loop: ; preds = %loop, %entry
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%tmp4 = phi i64 [ 0, %entry ], [ %tmp5, %loop ]
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%tmp5 = add i64 %tmp2, %tmp4
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%tmp6 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp5
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%tmp7 = load i8, i8 addrspace(1)* %tmp6, align 1
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%tmp8 = or i64 %tmp5, 1
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%tmp9 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp8
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%tmp10 = load i8, i8 addrspace(1)* %tmp9, align 1
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%tmp11 = add i8 %tmp7, %tmp10
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%tmp12 = sext i8 %tmp11 to i32
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store i32 %tmp12, i32 addrspace(1)* %out
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%tmp13 = icmp slt i64 %tmp5, 10
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br i1 %tmp13, label %loop, label %done
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done: ; preds = %loop
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ret void
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}
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; Test moving an SMRD instruction to the VALU
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; GCN-LABEL: {{^}}smrd_valu:
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; GCN: buffer_load_dword [[OUT:v[0-9]+]]
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; GCN: buffer_store_dword [[OUT]]
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define void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 {
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entry:
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%tmp = icmp ne i32 %a, 0
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br i1 %tmp, label %if, label %else
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if: ; preds = %entry
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%tmp1 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
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br label %endif
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else: ; preds = %entry
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%tmp2 = getelementptr i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
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%tmp3 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %tmp2
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br label %endif
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endif: ; preds = %else, %if
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%tmp4 = phi i32 addrspace(2)* [ %tmp1, %if ], [ %tmp3, %else ]
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%tmp5 = getelementptr i32, i32 addrspace(2)* %tmp4, i32 3000
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%tmp6 = load i32, i32 addrspace(2)* %tmp5
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store i32 %tmp6, i32 addrspace(1)* %out
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ret void
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}
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; Test moving an SMRD with an immediate offset to the VALU
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; GCN-LABEL: {{^}}smrd_valu2:
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; GCN: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
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define void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) #1 {
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entry:
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%tmp = call i32 @llvm.r600.read.tidig.x() #0
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%tmp1 = add i32 %tmp, 4
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%tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4
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%tmp3 = load i32, i32 addrspace(2)* %tmp2
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store i32 %tmp3, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}smrd_valu2_salu_user:
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; GCN: buffer_load_dword [[MOVED:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
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; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]]
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; GCN: buffer_store_dword [[ADD]]
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define void @smrd_valu2_salu_user(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in, i32 %a) #1 {
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entry:
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%tmp = call i32 @llvm.r600.read.tidig.x() #0
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%tmp1 = add i32 %tmp, 4
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%tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4
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%tmp3 = load i32, i32 addrspace(2)* %tmp2
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%tmp4 = add i32 %tmp3, %a
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store i32 %tmp4, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset:
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; GCN: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
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define void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 {
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entry:
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%tmp = call i32 @llvm.r600.read.tidig.x() #0
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%tmp1 = add i32 %tmp, 4
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%tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 255
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%tmp3 = load i32, i32 addrspace(2)* %tmp2
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store i32 %tmp3, i32 addrspace(1)* %out
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ret void
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}
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; Offset is too big to fit in SMRD 8-bit offset, but small enough to
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; fit in MUBUF offset.
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; FIXME: We should be using the offset but we don't
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; GCN-LABEL: {{^}}smrd_valu2_mubuf_offset:
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; GCN: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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define void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 {
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entry:
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%tmp = call i32 @llvm.r600.read.tidig.x() #0
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%tmp1 = add i32 %tmp, 4
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%tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 256
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%tmp3 = load i32, i32 addrspace(2)* %tmp2
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store i32 %tmp3, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_load_imm_v8i32:
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; GCN: buffer_load_dwordx4
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; GCN: buffer_load_dwordx4
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define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
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entry:
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%tmp0 = tail call i32 @llvm.r600.read.tidig.x()
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%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
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%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
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%tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4
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store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
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ret void
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}
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; GCN-LABEL: {{^}}s_load_imm_v8i32_salu_user:
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; GCN: buffer_load_dwordx4
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; GCN: buffer_load_dwordx4
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: buffer_store_dword
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define void @s_load_imm_v8i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
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entry:
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%tmp0 = tail call i32 @llvm.r600.read.tidig.x()
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%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
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%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
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%tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4
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%elt0 = extractelement <8 x i32> %tmp3, i32 0
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%elt1 = extractelement <8 x i32> %tmp3, i32 1
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%elt2 = extractelement <8 x i32> %tmp3, i32 2
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%elt3 = extractelement <8 x i32> %tmp3, i32 3
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%elt4 = extractelement <8 x i32> %tmp3, i32 4
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%elt5 = extractelement <8 x i32> %tmp3, i32 5
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%elt6 = extractelement <8 x i32> %tmp3, i32 6
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%elt7 = extractelement <8 x i32> %tmp3, i32 7
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%add0 = add i32 %elt0, %elt1
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%add1 = add i32 %add0, %elt2
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%add2 = add i32 %add1, %elt3
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%add3 = add i32 %add2, %elt4
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%add4 = add i32 %add3, %elt5
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%add5 = add i32 %add4, %elt6
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%add6 = add i32 %add5, %elt7
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store i32 %add6, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_load_imm_v16i32:
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; GCN: buffer_load_dwordx4
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; GCN: buffer_load_dwordx4
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; GCN: buffer_load_dwordx4
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; GCN: buffer_load_dwordx4
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define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
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entry:
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%tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
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%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
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%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
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%tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4
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store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
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ret void
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}
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; GCN-LABEL: {{^}}s_load_imm_v16i32_salu_user:
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; GCN: buffer_load_dwordx4
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; GCN: buffer_load_dwordx4
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; GCN: buffer_load_dwordx4
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; GCN: buffer_load_dwordx4
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: buffer_store_dword
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define void @s_load_imm_v16i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
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entry:
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%tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
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%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
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%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
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%tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4
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%elt0 = extractelement <16 x i32> %tmp3, i32 0
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%elt1 = extractelement <16 x i32> %tmp3, i32 1
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%elt2 = extractelement <16 x i32> %tmp3, i32 2
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%elt3 = extractelement <16 x i32> %tmp3, i32 3
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%elt4 = extractelement <16 x i32> %tmp3, i32 4
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%elt5 = extractelement <16 x i32> %tmp3, i32 5
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%elt6 = extractelement <16 x i32> %tmp3, i32 6
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%elt7 = extractelement <16 x i32> %tmp3, i32 7
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%elt8 = extractelement <16 x i32> %tmp3, i32 8
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%elt9 = extractelement <16 x i32> %tmp3, i32 9
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%elt10 = extractelement <16 x i32> %tmp3, i32 10
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%elt11 = extractelement <16 x i32> %tmp3, i32 11
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%elt12 = extractelement <16 x i32> %tmp3, i32 12
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%elt13 = extractelement <16 x i32> %tmp3, i32 13
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%elt14 = extractelement <16 x i32> %tmp3, i32 14
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%elt15 = extractelement <16 x i32> %tmp3, i32 15
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%add0 = add i32 %elt0, %elt1
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%add1 = add i32 %add0, %elt2
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%add2 = add i32 %add1, %elt3
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%add3 = add i32 %add2, %elt4
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%add4 = add i32 %add3, %elt5
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%add5 = add i32 %add4, %elt6
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%add6 = add i32 %add5, %elt7
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%add7 = add i32 %add6, %elt8
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%add8 = add i32 %add7, %elt9
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%add9 = add i32 %add8, %elt10
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%add10 = add i32 %add9, %elt11
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%add11 = add i32 %add10, %elt12
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%add12 = add i32 %add11, %elt13
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%add13 = add i32 %add12, %elt14
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%add14 = add i32 %add13, %elt15
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store i32 %add14, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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