forked from OSchip/llvm-project
124 lines
2.7 KiB
TableGen
124 lines
2.7 KiB
TableGen
//=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips32r6 instructions.
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//
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//===----------------------------------------------------------------------===//
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// Notes about removals/changes from MIPS32r6:
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// Unclear: ssnop
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// Reencoded: cache, pref
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// Reencoded: clo, clz
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// Reencoded: jr -> jalr
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// Reencoded: jr.hb -> jalr.hb
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// Reencoded: ldc2
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// Reencoded: ll, sc
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// Reencoded: lwc2
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// Reencoded: sdbbp
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// Reencoded: sdc2
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// Reencoded: swc2
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// Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
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// Removed: addi
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// Removed: bc1any2, bc1any4
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// Removed: bc2[ft]
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// Removed: bc2f, bc2t
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// Removed: bc[12][ft]l, bgezl, bgtzl, bgtzl, blezl, bltzall, bltzl, bnel, bgezall,
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// Removed: beql
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// Removed: bgezal
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// Removed: bltzal
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// Removed: c.cond.fmt, bc1[ft]
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// Removed: div, divu
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// Removed: jalx
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// Removed: ldxc1
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// Removed: luxc1
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// Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
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// Removed: lwxc1
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// Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
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// Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
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// Removed: movf, movt
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// Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
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// Removed: movn, movz
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// Removed: mult, multu
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// Removed: prefx
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// Removed: sdxc1
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// Removed: suxc1
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// Removed: swxc1
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// Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
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// Rencoded: [ls][wd]c2
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def ADDIUPC;
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def ALIGN; // Known as as BALIGN in DSP ASE
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def ALUIPC;
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def AUI;
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def AUIPC;
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def BALC;
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def BC1EQZ;
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def BC1NEZ;
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def BC2EQZ;
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def BC2NEZ;
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def BC;
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def BEQC;
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def BEQZALC;
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def BEQZC;
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def BGEC; // Also aliased to blec with operands swapped
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def BGEUC; // Also aliased to bleuc with operands swapped
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def BGEZALC;
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def BGEZC;
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def BGTZALC;
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def BGTZC;
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def BITSWAP; // Known as BITREV in DSP ASE
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def BLEZALC;
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def BLEZC;
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def BLTC; // Also aliased to bgtc with operands swapped
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def BLTUC; // Also aliased to bgtuc with operands swapped
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def BLTZALC;
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def BLTZC;
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def BNEC;
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def BNEZALC;
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def BNEZC;
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def BNVC;
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def BOVC;
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def CLASS_D;
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def CLASS_S;
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def CMP_CC_D;
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def CMP_CC_S;
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def DIV; // Not to be confused with the old div
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def DIVU; // Not to be confused with the old div
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def JIALC;
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def JIC;
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// def LSA; // See MSA
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def LWPC;
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def LWUPC;
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def MADDF;
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def MAXA_D;
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def MAXA_S;
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def MAX_D;
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def MAX_S;
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def MINA_D;
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def MINA_S;
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def MIN_D;
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def MOD;
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def MODU;
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def MSUBF;
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def MUH;
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def MUHU;
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def MUL_R6; // Not to be confused with the old mul
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def MULU;
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def NAL; // BAL with rd=0
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def RINT_D;
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def RINT_S;
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def SELEQZ;
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def SELEQZ_D;
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def SELEQZ_S;
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def SELNEZ;
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def SELNEZ_D;
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def SELNEZ_S;
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def SEL_D;
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def SEL_S;
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