.. |
AsmParser
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[RISCV][MC] Accept %lo and %pcrel_lo on operands to li
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2019-01-03 14:41:41 +00:00 |
Disassembler
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[RISCV] Support named operands for CSR instructions.
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2018-10-04 21:50:54 +00:00 |
InstPrinter
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[RISCV] Fix disassembling of fence instruction with invalid field
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2018-10-11 22:49:13 +00:00 |
MCTargetDesc
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[RISCV] Properly evaluate fixup_riscv_pcrel_lo12
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2018-12-20 14:52:15 +00:00 |
TargetInfo
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…
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Utils
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[RISCV][NFC] Define and use the new CA instruction format
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2018-11-16 10:33:23 +00:00 |
CMakeLists.txt
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[RISCV] Support named operands for CSR instructions.
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2018-10-04 21:50:54 +00:00 |
LLVMBuild.txt
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[RISCV] Support named operands for CSR instructions.
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2018-10-04 21:50:54 +00:00 |
RISCV.h
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[RISCV] Support named operands for CSR instructions.
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2018-10-04 21:50:54 +00:00 |
RISCV.td
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[RISCV] Support named operands for CSR instructions.
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2018-10-04 21:50:54 +00:00 |
RISCVAsmPrinter.cpp
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Revert "[RISCV] implement li pseudo instruction"
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2018-04-18 19:02:31 +00:00 |
RISCVCallingConv.td
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
RISCVExpandPseudoInsts.cpp
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[RISCV] Implement codegen for cmpxchg on RV32IA
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2018-11-29 20:43:42 +00:00 |
RISCVFrameLowering.cpp
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[RISCV] Fix std::advance slowness
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2018-08-24 23:13:59 +00:00 |
RISCVFrameLowering.h
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[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
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2018-03-20 01:39:17 +00:00 |
RISCVISelDAGToDAG.cpp
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[RISCV] Introduce codegen patterns for instructions introduced in RV64I
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2018-11-30 09:38:44 +00:00 |
RISCVISelLowering.cpp
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[RISCV] Add support for the various RISC-V FMA instruction variants
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2018-12-13 10:49:05 +00:00 |
RISCVISelLowering.h
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[TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V
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2018-11-30 09:56:54 +00:00 |
RISCVInstrFormats.td
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[RISCV][NFC] Define and use the new CA instruction format
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2018-11-16 10:33:23 +00:00 |
RISCVInstrFormatsC.td
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[RISCV][NFC] Define and use the new CA instruction format
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2018-11-16 10:33:23 +00:00 |
RISCVInstrInfo.cpp
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[RISCV] Remove overzealous is64Bit checks
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2018-10-04 14:30:03 +00:00 |
RISCVInstrInfo.h
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[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot
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2018-04-26 15:34:27 +00:00 |
RISCVInstrInfo.td
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[RISCV][MC] Accept %lo and %pcrel_lo on operands to li
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2019-01-03 14:41:41 +00:00 |
RISCVInstrInfoA.td
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[RISCV] Implement codegen for cmpxchg on RV32IA
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2018-11-29 20:43:42 +00:00 |
RISCVInstrInfoC.td
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[RISCV] Add UNIMP instruction (32- and 16-bit forms)
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2018-11-30 13:39:17 +00:00 |
RISCVInstrInfoD.td
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[RISCV] Add support for the various RISC-V FMA instruction variants
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2018-12-13 10:49:05 +00:00 |
RISCVInstrInfoF.td
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[RISCV] Add support for the various RISC-V FMA instruction variants
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2018-12-13 10:49:05 +00:00 |
RISCVInstrInfoM.td
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[RISCV] Codegen support for the standard RV32M instruction set extension
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2018-01-18 12:36:38 +00:00 |
RISCVMCInstLower.cpp
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[RISCV] Add codegen for RV32F floating point load/store
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2018-03-20 13:26:12 +00:00 |
RISCVMachineFunctionInfo.h
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[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv
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2018-04-12 05:34:25 +00:00 |
RISCVMergeBaseOffset.cpp
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Test commit.
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2018-08-02 05:38:18 +00:00 |
RISCVRegisterInfo.cpp
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
RISCVRegisterInfo.h
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[RISCV] Set isReMaterializable on ADDI and LUI instructions
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2018-05-17 15:51:37 +00:00 |
RISCVRegisterInfo.td
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[RISCV] Lower the tail pseudoinstruction
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2018-05-23 22:44:08 +00:00 |
RISCVSubtarget.cpp
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…
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RISCVSubtarget.h
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[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation
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2018-05-15 01:28:50 +00:00 |
RISCVSystemOperands.td
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[RISCV] Support named operands for CSR instructions.
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2018-10-04 21:50:54 +00:00 |
RISCVTargetMachine.cpp
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[Targets] Add errors for tiny and kernel codemodel on targets that don't support them
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2018-12-07 12:10:23 +00:00 |
RISCVTargetMachine.h
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…
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RISCVTargetObjectFile.cpp
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[RISCV] Use init_array instead of ctors for RISCV target, by default
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2018-03-24 18:37:19 +00:00 |
RISCVTargetObjectFile.h
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[RISCV] Use init_array instead of ctors for RISCV target, by default
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2018-03-24 18:37:19 +00:00 |