forked from OSchip/llvm-project
1c2927b209
If the parameters of the target cache (i.e., cache level sizes, cache level associativities) are not specified or have wrong values, we use ones for parameters of the macro-kernel and do not perform data-layout optimizations of the matrix multiplication. In this patch we specify the default values of the cache parameters to be able to apply the pattern matching optimizations even in this case. Since there is no typical values of this parameters, we use the parameters of Intel Core i7-3820 SandyBridge that also help to attain the high-performance on IBM POWER System S822 and IBM Power 730 Express server. Reviewed-by: Tobias Grosser <tobias@grosser.es> Differential Revision: https://reviews.llvm.org/D28090 llvm-svn: 290518 |
||
|---|---|---|
| .. | ||
| 2012-03-16-Empty-Domain.ll | ||
| 2012-04-16-Trivially-vectorizable-loops.ll | ||
| 2013-04-11-Empty-Domain-two.ll | ||
| computeout.ll | ||
| full_partial_tile_separation.ll | ||
| line-tiling-2.ll | ||
| line-tiling.ll | ||
| mat_mul_pattern_data_layout.ll | ||
| mat_mul_pattern_data_layout_2.ll | ||
| one-dimensional-band.ll | ||
| outer_coincidence.ll | ||
| pattern-matching-based-opts.ll | ||
| pattern-matching-based-opts_2.ll | ||
| pattern-matching-based-opts_3.ll | ||
| prevectorization-without-tiling.ll | ||
| prevectorization.ll | ||
| rectangular-tiling.ll | ||