forked from OSchip/llvm-project
126 lines
3.8 KiB
ArmAsm
126 lines
3.8 KiB
ArmAsm
// RUN: not llvm-mc -triple=thumbv8m.base -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK %s
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// RUN: FileCheck --check-prefix=UNDEF-BASELINE --check-prefix=UNDEF < %t %s
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// RUN: not llvm-mc -triple=thumbv8m.main -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK %s
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// RUN: FileCheck --check-prefix=UNDEF-MAINLINE --check-prefix=UNDEF < %t %s
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// Simple check that baseline is v6M and mainline is v7M
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// UNDEF-BASELINE: error: instruction requires: thumb2
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// UNDEF-MAINLINE-NOT: error: instruction requires:
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mov.w r0, r0
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// Check that .arm is invalid
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// UNDEF: target does not support ARM mode
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.arm
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// Instruction availibility checks
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// 'Barrier instructions'
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// CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
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isb sy
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// 'Code optimization'
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// CHECK: cbz r3, .Ltmp0 @ encoding: [0x03'A',0xb1'A']
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// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb
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cbz r3, 1f
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// CHECK: cbnz r3, .Ltmp0 @ encoding: [0x03'A',0xb9'A']
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// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb
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cbnz r3, 1f
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// CHECK: b.w .Ltmp0 @ encoding: [A,0xf0'A',A,0x90'A']
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// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_t2_uncondbranch
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b.w 1f
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// CHECK: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
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sdiv r1, r2, r3
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// CHECK: udiv r1, r2, r3 @ encoding: [0xb2,0xfb,0xf3,0xf1]
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udiv r1, r2, r3
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// 'Exclusives from ARMv7-M'
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// CHECK: clrex @ encoding: [0xbf,0xf3,0x2f,0x8f]
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clrex
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// CHECK: ldrex r1, [r2, #4] @ encoding: [0x52,0xe8,0x01,0x1f]
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ldrex r1, [r2, #4]
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// CHECK: ldrexb r1, [r2] @ encoding: [0xd2,0xe8,0x4f,0x1f]
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ldrexb r1, [r2]
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// CHECK: ldrexh r1, [r2] @ encoding: [0xd2,0xe8,0x5f,0x1f]
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ldrexh r1, [r2]
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// UNDEF-BASELINE: error: instruction requires: !armv*m thumb2
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// UNDEF-MAINLINE: error: instruction requires: !armv*m
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ldrexd r0, r1, [r2]
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// CHECK: strex r1, r2, [r3, #4] @ encoding: [0x43,0xe8,0x01,0x21]
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strex r1, r2, [r3, #4]
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// CHECK: strexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0x41,0x2f]
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strexb r1, r2, [r3]
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// CHECK: strexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0x51,0x2f]
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strexh r1, r2, [r3]
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// UNDEF-BASELINE: error: instruction requires: !armv*m thumb2
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// UNDEF-MAINLINE: error: instruction requires: !armv*m
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strexd r0, r1, r2, [r3]
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// 'XO generation'
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// CHECK: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71]
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movw r1, #0xffff
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// CHECK: movt r1, #65535 @ encoding: [0xcf,0xf6,0xff,0x71]
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movt r1, #0xffff
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// 'Acquire/Release from ARMv8-A'
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// CHECK: lda r1, [r2] @ encoding: [0xd2,0xe8,0xaf,0x1f]
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lda r1, [r2]
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// CHECK: ldab r1, [r2] @ encoding: [0xd2,0xe8,0x8f,0x1f]
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ldab r1, [r2]
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// CHECK: ldah r1, [r2] @ encoding: [0xd2,0xe8,0x9f,0x1f]
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ldah r1, [r2]
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// CHECK: stl r1, [r3] @ encoding: [0xc3,0xe8,0xaf,0x1f]
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stl r1, [r3]
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// CHECK: stlb r1, [r3] @ encoding: [0xc3,0xe8,0x8f,0x1f]
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stlb r1, [r3]
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// CHECK: stlh r1, [r3] @ encoding: [0xc3,0xe8,0x9f,0x1f]
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stlh r1, [r3]
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// CHECK: ldaex r1, [r2] @ encoding: [0xd2,0xe8,0xef,0x1f]
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ldaex r1, [r2]
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// CHECK: ldaexb r1, [r2] @ encoding: [0xd2,0xe8,0xcf,0x1f]
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ldaexb r1, [r2]
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// CHECK: ldaexh r1, [r2] @ encoding: [0xd2,0xe8,0xdf,0x1f]
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ldaexh r1, [r2]
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// UNDEF: error: instruction requires: !armv*m
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ldaexd r0, r1, [r2]
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// CHECK: stlex r1, r2, [r3] @ encoding: [0xc3,0xe8,0xe1,0x2f]
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stlex r1, r2, [r3]
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// CHECK: stlexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0xc1,0x2f]
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stlexb r1, r2, [r3]
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// CHECK: stlexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0xd1,0x2f]
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stlexh r1, r2, [r3]
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// UNDEF: error: instruction requires: !armv*m
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stlexd r0, r1, r2, [r2]
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