forked from OSchip/llvm-project
185 lines
4.7 KiB
LLVM
185 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi | FileCheck %s -check-prefix=LE
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; RUN: llc < %s -mtriple=armeb-eabi | FileCheck %s -check-prefix=BE
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define void @i24_or(i24* %a) {
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; LE-LABEL: i24_or:
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; LE: @ BB#0:
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; LE-NEXT: ldrh r1, [r0]
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; LE-NEXT: orr r1, r1, #384
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; LE-NEXT: strh r1, [r0]
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i24_or:
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; BE: @ BB#0:
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; BE-NEXT: ldrh r1, [r0]
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; BE-NEXT: ldrb r2, [r0, #2]
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; BE-NEXT: orr r1, r2, r1, lsl #8
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; BE-NEXT: orr r1, r1, #384
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; BE-NEXT: strb r1, [r0, #2]
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; BE-NEXT: lsr r1, r1, #8
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; BE-NEXT: strh r1, [r0]
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; BE-NEXT: mov pc, lr
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%aa = load i24, i24* %a, align 1
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%b = or i24 %aa, 384
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store i24 %b, i24* %a, align 1
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ret void
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}
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define void @i24_and_or(i24* %a) {
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; LE-LABEL: i24_and_or:
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; LE: @ BB#0:
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; LE-NEXT: ldrh r1, [r0]
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; LE-NEXT: mov r2, #16256
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; LE-NEXT: orr r2, r2, #49152
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; LE-NEXT: orr r1, r1, #384
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; LE-NEXT: and r1, r1, r2
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; LE-NEXT: strh r1, [r0]
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i24_and_or:
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; BE: @ BB#0:
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; BE-NEXT: mov r1, #128
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; BE-NEXT: strb r1, [r0, #2]
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; BE-NEXT: ldrh r1, [r0]
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; BE-NEXT: orr r1, r1, #1
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; BE-NEXT: strh r1, [r0]
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; BE-NEXT: mov pc, lr
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%b = load i24, i24* %a, align 1
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%c = and i24 %b, -128
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%d = or i24 %c, 384
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store i24 %d, i24* %a, align 1
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ret void
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}
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define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
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; LE-LABEL: i24_insert_bit:
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; LE: @ BB#0:
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; LE-NEXT: mov r3, #255
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; LE-NEXT: ldrh r2, [r0]
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; LE-NEXT: orr r3, r3, #57088
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; LE-NEXT: and r2, r2, r3
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; LE-NEXT: orr r1, r2, r1, lsl #13
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; LE-NEXT: strh r1, [r0]
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i24_insert_bit:
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; BE: @ BB#0:
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; BE-NEXT: ldrh r2, [r0]
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; BE-NEXT: mov r3, #57088
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; BE-NEXT: orr r3, r3, #16711680
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; BE-NEXT: and r2, r3, r2, lsl #8
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; BE-NEXT: orr r1, r2, r1, lsl #13
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; BE-NEXT: lsr r1, r1, #8
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; BE-NEXT: strh r1, [r0]
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; BE-NEXT: mov pc, lr
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%extbit = zext i1 %bit to i24
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%b = load i24, i24* %a, align 1
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%extbit.shl = shl nuw nsw i24 %extbit, 13
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%c = and i24 %b, -8193
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%d = or i24 %c, %extbit.shl
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store i24 %d, i24* %a, align 1
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ret void
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}
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define void @i56_or(i56* %a) {
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; LE-LABEL: i56_or:
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; LE: @ BB#0:
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; LE-NEXT: ldr r1, [r0]
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; LE-NEXT: orr r1, r1, #384
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; LE-NEXT: str r1, [r0]
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i56_or:
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; BE: @ BB#0:
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; BE-NEXT: mov r1, r0
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; BE-NEXT: ldr r12, [r0]
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; BE-NEXT: ldrh r2, [r1, #4]!
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; BE-NEXT: ldrb r3, [r1, #2]
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; BE-NEXT: orr r2, r3, r2, lsl #8
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; BE-NEXT: orr r2, r2, r12, lsl #24
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; BE-NEXT: orr r2, r2, #384
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; BE-NEXT: strb r2, [r1, #2]
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; BE-NEXT: lsr r3, r2, #8
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; BE-NEXT: strh r3, [r1]
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; BE-NEXT: bic r1, r12, #255
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; BE-NEXT: orr r1, r1, r2, lsr #24
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; BE-NEXT: str r1, [r0]
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; BE-NEXT: mov pc, lr
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%aa = load i56, i56* %a
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%b = or i56 %aa, 384
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store i56 %b, i56* %a
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ret void
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}
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define void @i56_and_or(i56* %a) {
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; LE-LABEL: i56_and_or:
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; LE: @ BB#0:
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; LE-NEXT: ldr r1, [r0]
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; LE-NEXT: orr r1, r1, #384
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; LE-NEXT: bic r1, r1, #127
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; LE-NEXT: str r1, [r0]
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i56_and_or:
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; BE: @ BB#0:
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; BE-NEXT: mov r1, r0
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; BE-NEXT: ldr r12, [r0]
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; BE-NEXT: ldrh r2, [r1, #4]!
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; BE-NEXT: mov r3, #128
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; BE-NEXT: strb r3, [r1, #2]
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; BE-NEXT: lsl r2, r2, #8
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; BE-NEXT: orr r2, r2, r12, lsl #24
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; BE-NEXT: orr r2, r2, #384
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; BE-NEXT: lsr r3, r2, #8
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; BE-NEXT: strh r3, [r1]
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; BE-NEXT: bic r1, r12, #255
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; BE-NEXT: orr r1, r1, r2, lsr #24
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; BE-NEXT: str r1, [r0]
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; BE-NEXT: mov pc, lr
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%b = load i56, i56* %a, align 1
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%c = and i56 %b, -128
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%d = or i56 %c, 384
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store i56 %d, i56* %a, align 1
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ret void
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}
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define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
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; LE-LABEL: i56_insert_bit:
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; LE: @ BB#0:
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; LE-NEXT: ldr r2, [r0]
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; LE-NEXT: bic r2, r2, #8192
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; LE-NEXT: orr r1, r2, r1, lsl #13
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; LE-NEXT: str r1, [r0]
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i56_insert_bit:
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; BE: @ BB#0:
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; BE-NEXT: .save {r11, lr}
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; BE-NEXT: push {r11, lr}
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; BE-NEXT: mov r2, r0
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; BE-NEXT: ldr lr, [r0]
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; BE-NEXT: ldrh r12, [r2, #4]!
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; BE-NEXT: ldrb r3, [r2, #2]
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; BE-NEXT: orr r12, r3, r12, lsl #8
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; BE-NEXT: orr r3, r12, lr, lsl #24
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; BE-NEXT: bic r3, r3, #8192
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; BE-NEXT: orr r1, r3, r1, lsl #13
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; BE-NEXT: lsr r3, r1, #8
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; BE-NEXT: strh r3, [r2]
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; BE-NEXT: bic r2, lr, #255
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; BE-NEXT: orr r1, r2, r1, lsr #24
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; BE-NEXT: str r1, [r0]
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; BE-NEXT: pop {r11, lr}
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; BE-NEXT: mov pc, lr
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%extbit = zext i1 %bit to i56
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%b = load i56, i56* %a, align 1
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%extbit.shl = shl nuw nsw i56 %extbit, 13
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%c = and i56 %b, -8193
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%d = or i56 %c, %extbit.shl
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store i56 %d, i56* %a, align 1
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ret void
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}
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