forked from OSchip/llvm-project
172 lines
6.1 KiB
C++
172 lines
6.1 KiB
C++
//===--- AArch64StorePairSuppress.cpp --- Suppress store pair formation ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass identifies floating point stores that should not be combined into
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// store pairs. Later we may do the same for floating point loads.
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// ===---------------------------------------------------------------------===//
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#include "AArch64InstrInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineTraceMetrics.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-stp-suppress"
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#define STPSUPPRESS_PASS_NAME "AArch64 Store Pair Suppression"
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namespace {
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class AArch64StorePairSuppress : public MachineFunctionPass {
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const AArch64InstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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TargetSchedModel SchedModel;
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MachineTraceMetrics *Traces;
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MachineTraceMetrics::Ensemble *MinInstr;
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public:
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static char ID;
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AArch64StorePairSuppress() : MachineFunctionPass(ID) {
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initializeAArch64StorePairSuppressPass(*PassRegistry::getPassRegistry());
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}
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StringRef getPassName() const override { return STPSUPPRESS_PASS_NAME; }
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bool runOnMachineFunction(MachineFunction &F) override;
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private:
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bool shouldAddSTPToBlock(const MachineBasicBlock *BB);
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bool isNarrowFPStore(const MachineInstr &MI);
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineTraceMetrics>();
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AU.addPreserved<MachineTraceMetrics>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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char AArch64StorePairSuppress::ID = 0;
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} // anonymous
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INITIALIZE_PASS(AArch64StorePairSuppress, "aarch64-stp-suppress",
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STPSUPPRESS_PASS_NAME, false, false)
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FunctionPass *llvm::createAArch64StorePairSuppressPass() {
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return new AArch64StorePairSuppress();
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}
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/// Return true if an STP can be added to this block without increasing the
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/// critical resource height. STP is good to form in Ld/St limited blocks and
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/// bad to form in float-point limited blocks. This is true independent of the
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/// critical path. If the critical path is longer than the resource height, the
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/// extra vector ops can limit physreg renaming. Otherwise, it could simply
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/// oversaturate the vector units.
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bool AArch64StorePairSuppress::shouldAddSTPToBlock(const MachineBasicBlock *BB) {
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if (!MinInstr)
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MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
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MachineTraceMetrics::Trace BBTrace = MinInstr->getTrace(BB);
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unsigned ResLength = BBTrace.getResourceLength();
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// Get the machine model's scheduling class for STPQi.
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// Bypass TargetSchedule's SchedClass resolution since we only have an opcode.
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unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
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const MCSchedClassDesc *SCDesc =
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SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx);
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// If a subtarget does not define resources for STPQi, bail here.
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if (SCDesc->isValid() && !SCDesc->isVariant()) {
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unsigned ResLenWithSTP = BBTrace.getResourceLength(None, SCDesc);
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if (ResLenWithSTP > ResLength) {
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LLVM_DEBUG(dbgs() << " Suppress STP in BB: " << BB->getNumber()
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<< " resources " << ResLength << " -> " << ResLenWithSTP
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<< "\n");
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return false;
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}
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}
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return true;
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}
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/// Return true if this is a floating-point store smaller than the V reg. On
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/// cyclone, these require a vector shuffle before storing a pair.
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/// Ideally we would call getMatchingPairOpcode() and have the machine model
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/// tell us if it's profitable with no cpu knowledge here.
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///
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/// FIXME: We plan to develop a decent Target abstraction for simple loads and
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/// stores. Until then use a nasty switch similar to AArch64LoadStoreOptimizer.
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bool AArch64StorePairSuppress::isNarrowFPStore(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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default:
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return false;
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case AArch64::STRSui:
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case AArch64::STRDui:
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case AArch64::STURSi:
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case AArch64::STURDi:
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return true;
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}
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}
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bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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const TargetSubtargetInfo &ST = MF.getSubtarget();
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TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());
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TRI = ST.getRegisterInfo();
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MRI = &MF.getRegInfo();
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SchedModel.init(&ST);
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Traces = &getAnalysis<MachineTraceMetrics>();
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MinInstr = nullptr;
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LLVM_DEBUG(dbgs() << "*** " << getPassName() << ": " << MF.getName() << '\n');
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if (!SchedModel.hasInstrSchedModel()) {
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LLVM_DEBUG(dbgs() << " Skipping pass: no machine model present.\n");
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return false;
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}
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// Check for a sequence of stores to the same base address. We don't need to
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// precisely determine whether a store pair can be formed. But we do want to
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// filter out most situations where we can't form store pairs to avoid
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// computing trace metrics in those cases.
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for (auto &MBB : MF) {
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bool SuppressSTP = false;
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unsigned PrevBaseReg = 0;
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for (auto &MI : MBB) {
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if (!isNarrowFPStore(MI))
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continue;
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unsigned BaseReg;
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int64_t Offset;
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if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) {
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if (PrevBaseReg == BaseReg) {
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// If this block can take STPs, skip ahead to the next block.
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if (!SuppressSTP && shouldAddSTPToBlock(MI.getParent()))
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break;
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// Otherwise, continue unpairing the stores in this block.
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LLVM_DEBUG(dbgs() << "Unpairing store " << MI << "\n");
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SuppressSTP = true;
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TII->suppressLdStPair(MI);
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}
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PrevBaseReg = BaseReg;
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} else
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PrevBaseReg = 0;
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}
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}
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// This pass just sets some internal MachineMemOperand flags. It can't really
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// invalidate anything.
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return false;
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}
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