llvm-project/llvm/test/CodeGen/MSP430
Sanjay Patel 288079aafd [DAGCombiner] add operation legality checks before creating shift ops (PR43542)
As discussed on llvm-dev and:
https://bugs.llvm.org/show_bug.cgi?id=43542
...we have transforms that assume shift operations are legal and transforms to
use them are profitable, but that may not hold for simple targets.

In this case, the MSP430 target custom lowers shifts by repeating (many)
simpler/fixed ops. That can be avoided by keeping this code as setcc/select.

Differential Revision: https://reviews.llvm.org/D68397

llvm-svn: 373666
2019-10-03 21:34:04 +00:00
..
2009-05-10-CyclicDAG.ll
2009-05-17-Rot.ll
2009-05-17-Shift.ll
2009-05-19-DoubleSplit.ll
2009-08-25-DynamicStackAlloc.ll
2009-09-18-AbsoluteAddr.ll
2009-10-10-OrImpDef.ll
2009-11-08-InvalidResNo.ll
2009-11-20-NewNode.ll
2009-12-21-FrameAddr.ll
2009-12-22-InlineAsm.ll
2010-05-01-CombinerAnd.ll
AddrMode-bis-rx.ll
AddrMode-bis-xr.ll
AddrMode-mov-rx.ll
AddrMode-mov-xr.ll
BranchSelector.ll
DbgValueOtherTargets.test
Inst8mi.ll
Inst8mm.ll
Inst8mr.ll
Inst8ri.ll
Inst8rm.ll
Inst8rr.ll
Inst16mi.ll
Inst16mm.ll
Inst16mr.ll
Inst16ri.ll
Inst16rm.ll
Inst16rr.ll
InstII.ll
asm-clobbers.ll
bit.ll
byval.ll
callee-saved.ll
calls.ll
cc_args.ll
cc_ret.ll
flt_rounds.ll
fp.ll
hwmult16.ll
hwmult32.ll
hwmultf5.ll
indirectbr.ll
indirectbr2.ll
inline-asm-absolute-addressing.ll
inline-asm.ll
inlineasm-output-template.ll [AsmPrinter] refactor to support %c w/ GlobalAddress' 2019-04-26 18:45:04 +00:00
interrupt.ll [MSP430] Allow msp430_intrcc functions to not have interrupt attribute. 2019-09-25 18:58:07 +00:00
jumptable.ll
libcalls.ll
lit.local.cfg [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
memset.ll
misched-msp430.ll
mult-alt-generic-msp430.ll
postinc.ll
promote-i8-mul.ll
select-use-sr.ll
selectcc.ll [DAGCombiner] add operation legality checks before creating shift ops (PR43542) 2019-10-03 21:34:04 +00:00
setcc.ll
shifts.ll
spill-to-stack.ll
stacksave_restore.ll
struct-return.ll
struct_layout.ll
transient-stack-alignment.ll
umulo-16.ll
vararg.ll