forked from OSchip/llvm-project
33 lines
1.0 KiB
LLVM
33 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=1 < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}spill_csr_s5_copy:
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; GCN: s_or_saveexec_b64
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; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec
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; GCN: v_writelane_b32 v32, s34, 2
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; GCN: s_swappc_b64
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 9
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; GCN: buffer_store_dword [[K]], off, s[0:3], s34{{$}}
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; GCN: v_readlane_b32 s34, v32, 2
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; GCN: s_or_saveexec_b64
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; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
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; GCN: s_mov_b64 exec
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; GCN: s_setpc_b64
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define void @spill_csr_s5_copy() #0 {
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bb:
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%alloca = alloca i32, addrspace(5)
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%tmp = tail call i64 @func() #1
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* null, i64 %tmp
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%tmp2 = load i32, i32 addrspace(1)* %tmp1, align 4
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%tmp3 = zext i32 %tmp2 to i64
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store volatile i32 9, i32 addrspace(5)* %alloca
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ret void
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}
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declare i64 @func()
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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