forked from OSchip/llvm-project
131 lines
5.1 KiB
LLVM
131 lines
5.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX678,HAS-ATOMICS %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,HAS-ATOMICS %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX678,NO-ATOMICS %s
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; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX678,NO-ATOMICS %s
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; GCN-LABEL: {{^}}lds_atomic_fadd_ret_f32:
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; GFX678-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; HAS-ATOMICS-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 4.0
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; HAS-ATOMICS: ds_add_rtn_f32 v0, v0, [[K]]
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; NO-ATOMICS: ds_read_b32
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; NO-ATOMICS: v_add_f32
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; NO-ATOMICS: ds_cmpst_rtn_b32
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; NO-ATOMICS: s_cbranch_execnz
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define float @lds_atomic_fadd_ret_f32(float addrspace(3)* %ptr) nounwind {
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%result = atomicrmw fadd float addrspace(3)* %ptr, float 4.0 seq_cst
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ret float %result
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}
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; GCN-LABEL: {{^}}lds_atomic_fadd_noret_f32:
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; GFX678-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; HAS-ATOMICS-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 4.0
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; HAS-ATOMICS: ds_add_f32 v0, [[K]]
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define void @lds_atomic_fadd_noret_f32(float addrspace(3)* %ptr) nounwind {
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%result = atomicrmw fadd float addrspace(3)* %ptr, float 4.0 seq_cst
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ret void
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}
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; GCN-LABEL: {{^}}lds_ds_fadd:
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; VI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; HAS-ATOMICS-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
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; HAS-ATOMICS: ds_add_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32
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; HAS-ATOMICS: ds_add_f32 [[V3:v[0-9]+]], [[V0]] offset:64
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; HAS-ATOMICS: s_waitcnt vmcnt(0) lgkmcnt(0)
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; HAS-ATOMICS: ds_add_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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define amdgpu_kernel void @lds_ds_fadd(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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%idx.add = add nuw i32 %idx, 4
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%shl0 = shl i32 %idx.add, 3
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%shl1 = shl i32 %idx.add, 4
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%ptr0 = inttoptr i32 %shl0 to float addrspace(3)*
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%ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
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%a1 = atomicrmw fadd float addrspace(3)* %ptr0, float 4.2e+1 seq_cst
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%a2 = atomicrmw fadd float addrspace(3)* %ptr1, float 4.2e+1 seq_cst
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%a3 = atomicrmw fadd float addrspace(3)* %ptrf, float %a1 seq_cst
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store float %a3, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}lds_ds_fadd_one_as:
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; VI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; HAS-ATOMICS-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
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; HAS-ATOMICS: ds_add_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32
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; HAS-ATOMICS: ds_add_f32 [[V3:v[0-9]+]], [[V0]] offset:64
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; HAS-ATOMICS: s_waitcnt lgkmcnt(1)
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; HAS-ATOMICS: ds_add_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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define amdgpu_kernel void @lds_ds_fadd_one_as(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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%idx.add = add nuw i32 %idx, 4
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%shl0 = shl i32 %idx.add, 3
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%shl1 = shl i32 %idx.add, 4
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%ptr0 = inttoptr i32 %shl0 to float addrspace(3)*
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%ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
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%a1 = atomicrmw fadd float addrspace(3)* %ptr0, float 4.2e+1 syncscope("one-as") seq_cst
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%a2 = atomicrmw fadd float addrspace(3)* %ptr1, float 4.2e+1 syncscope("one-as") seq_cst
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%a3 = atomicrmw fadd float addrspace(3)* %ptrf, float %a1 syncscope("one-as") seq_cst
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store float %a3, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_fadd_ret_f64:
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; GCN: ds_read_b64
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; GCN: v_add_f64
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; GCN: ds_cmpst_rtn_b64
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; GCN: s_cbranch_execnz
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define double @lds_atomic_fadd_ret_f64(double addrspace(3)* %ptr) nounwind {
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%result = atomicrmw fadd double addrspace(3)* %ptr, double 4.0 seq_cst
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ret double %result
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}
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; GCN-LABEL: {{^}}lds_atomic_fadd_noret_f64:
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; GCN: ds_read_b64
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; GCN: v_add_f64
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; GCN: ds_cmpst_rtn_b64
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; GCN: s_cbranch_execnz
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define void @lds_atomic_fadd_noret_f64(double addrspace(3)* %ptr) nounwind {
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%result = atomicrmw fadd double addrspace(3)* %ptr, double 4.0 seq_cst
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_fsub_ret_f32:
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; GCN: ds_read_b32
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; GCN: v_sub_f32
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; GCN: ds_cmpst_rtn_b32
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; GCN: s_cbranch_execnz
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define float @lds_atomic_fsub_ret_f32(float addrspace(3)* %ptr, float %val) nounwind {
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%result = atomicrmw fsub float addrspace(3)* %ptr, float %val seq_cst
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ret float %result
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}
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; GCN-LABEL: {{^}}lds_atomic_fsub_noret_f32:
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; GCN: ds_read_b32
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; GCN: v_sub_f32
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; GCN: ds_cmpst_rtn_b32
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define void @lds_atomic_fsub_noret_f32(float addrspace(3)* %ptr, float %val) nounwind {
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%result = atomicrmw fsub float addrspace(3)* %ptr, float %val seq_cst
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_fsub_ret_f64:
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; GCN: ds_read_b64
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; GCN: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+:[0-9]+\]}}
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; GCN: ds_cmpst_rtn_b64
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define double @lds_atomic_fsub_ret_f64(double addrspace(3)* %ptr, double %val) nounwind {
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%result = atomicrmw fsub double addrspace(3)* %ptr, double %val seq_cst
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ret double %result
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}
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; GCN-LABEL: {{^}}lds_atomic_fsub_noret_f64:
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; GCN: ds_read_b64
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; GCN: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+:[0-9]+\]}}
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; GCN: ds_cmpst_rtn_b64
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; GCN: s_cbranch_execnz
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define void @lds_atomic_fsub_noret_f64(double addrspace(3)* %ptr, double %val) nounwind {
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%result = atomicrmw fsub double addrspace(3)* %ptr, double %val seq_cst
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ret void
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}
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