forked from OSchip/llvm-project
197 lines
5.7 KiB
LLVM
197 lines
5.7 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null -fp-contract=fast | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FAST
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; Check latencies of vmul/vfma accumulate chains.
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define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test1:%bb.0
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; CHECK: VMULS
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; > VMULS common latency = 5
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; CHECK: Latency : 5
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; CHECK: Successors:
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; CHECK: Data
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; > VMULS read-advanced latency to VMLAS = 0
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; CHECK-SAME: Latency=0
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; CHECK-DEFAULT: VMLAS
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; CHECK-FAST: VFMAS
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; > VMLAS common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLAS read-advanced latency to the next VMLAS = 4
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; CHECK-SAME: Latency=4
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; CHECK-DEFAULT: VMLAS
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; CHECK-FAST: VFMAS
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLAS not-optimized latency to VMOVRS = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS
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%mul1 = fmul float %f1, %f2
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%mul2 = fmul float %f3, %f4
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%mul3 = fmul float %f5, %f6
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%add1 = fadd float %mul1, %mul2
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%add2 = fadd float %add1, %mul3
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ret float %add2
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}
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; ASIMD form
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define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test2:%bb.0
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; CHECK: VMULfd
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; > VMULfd common latency = 5
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; CHECK: Latency : 5
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; CHECK: Successors:
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; CHECK: Data
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; VMULfd read-advanced latency to VMLAfd = 0
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; CHECK-SAME: Latency=0
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; CHECK-DEFAULT: VMLAfd
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; CHECK-FAST: VFMAfd
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; > VMLAfd common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLAfd read-advanced latency to the next VMLAfd = 4
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; CHECK-SAME: Latency=4
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; CHECK-DEFAULT: VMLAfd
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; CHECK-FAST: VFMAfd
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLAfd not-optimized latency to VMOVRRD = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS
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%mul1 = fmul <2 x float> %f1, %f2
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%mul2 = fmul <2 x float> %f3, %f4
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%mul3 = fmul <2 x float> %f5, %f6
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%add1 = fadd <2 x float> %mul1, %mul2
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%add2 = fadd <2 x float> %add1, %mul3
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ret <2 x float> %add2
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}
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define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test3:%bb.0
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; CHECK: VMULS
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; > VMULS common latency = 5
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; CHECK: Latency : 5
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; CHECK: Successors:
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; CHECK: Data
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; > VMULS read-advanced latency to VMLSS = 0
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; CHECK-SAME: Latency=0
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; CHECK-DEFAULT: VMLSS
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; CHECK-FAST: VFMSS
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; > VMLSS common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLSS read-advanced latency to the next VMLSS = 4
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; CHECK-SAME: Latency=4
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; CHECK-DEFAULT: VMLSS
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; CHECK-FAST: VFMSS
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLSS not-optimized latency to VMOVRS = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLSS, VMLSS
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%mul1 = fmul float %f1, %f2
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%mul2 = fmul float %f3, %f4
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%mul3 = fmul float %f5, %f6
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%sub1 = fsub float %mul1, %mul2
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%sub2 = fsub float %sub1, %mul3
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ret float %sub2
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}
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; ASIMD form
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define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test4:%bb.0
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; CHECK: VMULfd
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; > VMULfd common latency = 5
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; CHECK: Latency : 5
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; CHECK: Successors:
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; CHECK: Data
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; VMULfd read-advanced latency to VMLSfd = 0
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; CHECK-SAME: Latency=0
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; CHECK-DEFAULT: VMLSfd
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; CHECK-FAST: VFMSfd
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; > VMLSfd common latency = 9
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLSfd read-advanced latency to the next VMLSfd = 4
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; CHECK-SAME: Latency=4
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; CHECK-DEFAULT: VMLSfd
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; CHECK-FAST: VFMSfd
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLSfd not-optimized latency to VMOVRRD = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLSS, VMLSS
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%mul1 = fmul <2 x float> %f1, %f2
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%mul2 = fmul <2 x float> %f3, %f4
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%mul3 = fmul <2 x float> %f5, %f6
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%sub1 = fsub <2 x float> %mul1, %mul2
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%sub2 = fsub <2 x float> %sub1, %mul3
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ret <2 x float> %sub2
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}
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define float @Test5(float %f1, float %f2, float %f3) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test5:%bb.0
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; CHECK-DEFAULT: VNMLS
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; CHECK-FAST: VFNMS
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLAS not-optimized latency to VMOVRS = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 - f3 ==> VNMLS/VFNMS
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%mul = fmul float %f1, %f2
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%sub = fsub float %mul, %f3
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ret float %sub
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}
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define float @Test6(float %f1, float %f2, float %f3) {
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; CHECK: ********** MI Scheduling **********
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; CHECK: Test6:%bb.0
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; CHECK-DEFAULT: VNMLA
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; CHECK-FAST: VFNMA
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; CHECK: Latency : 9
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; CHECK: Successors:
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; CHECK: Data
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; > VMLAS not-optimized latency to VMOVRS = 9
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; CHECK-SAME: Latency=9
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; f1 * f2 - f3 ==> VNMLA/VFNMA
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%mul = fmul float %f1, %f2
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%sub1 = fsub float -0.0, %mul
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%sub2 = fsub float %sub1, %f2
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ret float %sub2
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}
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