forked from OSchip/llvm-project
40 lines
1.2 KiB
LLVM
40 lines
1.2 KiB
LLVM
; RUN: llc < %s -o /dev/null "-mtriple=thumbv7-apple-ios" -debug-only=post-RA-sched 2> %t
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; RUN: FileCheck %s < %t
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; REQUIRES: asserts
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; Make sure that mayalias store-load dependencies have one cycle
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; latency regardless of whether they are barriers or not.
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; CHECK: ** List Scheduling
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; CHECK: SU(2){{.*}}STR{{.*}}(volatile
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; CHECK-NOT: SU({{.*}}): Ord
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; CHECK: SU(3): Ord Latency=1
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; CHECK-NOT: SU({{.*}}): Ord
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; CHECK: SU(3){{.*}}LDR{{.*}}(volatile
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; CHECK-NOT: SU({{.*}}): Ord
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; CHECK: SU(2): Ord Latency=1
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; CHECK-NOT: SU({{.*}}): Ord
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; CHECK: Successors:
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; CHECK: ** List Scheduling
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; CHECK: SU(2){{.*}}STR{{.*}}
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; CHECK-NOT: SU({{.*}}): Ord
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; CHECK: SU(3): Ord Latency=1
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; CHECK-NOT: SU({{.*}}): Ord
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; CHECK: SU(3){{.*}}LDR{{.*}}
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; CHECK-NOT: SU({{.*}}): Ord
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; CHECK: SU(2): Ord Latency=1
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; CHECK-NOT: SU({{.*}}): Ord
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; CHECK: Successors:
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define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind {
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entry:
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store volatile i32 65540, i32* %p1, align 4
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%0 = load volatile i32, i32* %p2, align 4
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ret i32 %0
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}
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define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind {
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entry:
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store i32 65540, i32* %p1, align 4
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%0 = load i32, i32* %p2, align 4
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ret i32 %0
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}
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