forked from OSchip/llvm-project
63 lines
2.0 KiB
TableGen
63 lines
2.0 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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def int_mytarget_sleep : Intrinsic<[], [llvm_i32_ty], [ImmArg<0>]>;
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def G_TGT_CAT : MyTargetGenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type1:$src0, untyped_imm_0:$immfield);
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}
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def TgtCat : SDNode<"MyTgt::CAT", SDTIntBinOp>;
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def : GINodeEquiv<G_TGT_CAT, TgtCat>;
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def SLEEP0 : I<(outs), (ins), []>;
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def SLEEP1 : I<(outs), (ins), []>;
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def CAT0 : I<(outs GPR32:$dst), (ins GPR32:$src0), []>;
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def CAT1 : I<(outs GPR32:$dst), (ins GPR32:$src0), []>;
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// Test immarg intrinsic pattern
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// Make sure there is no type check.
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// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS,
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// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep,
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// GISEL-NEXT: // MIs[0] Operand 1
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// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 0,
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def : Pat<
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(int_mytarget_sleep 0),
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(SLEEP0)
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>;
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// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS,
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// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep,
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// GISEL-NEXT: // MIs[0] Operand 1
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// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 1,
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def : Pat<
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(int_mytarget_sleep 1),
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(SLEEP1)
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>;
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// Check a non-intrinsic instruction with an immediate parameter.
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// GISEL: GIM_CheckOpcode, /*MI*/0, MyTarget::G_TGT_CAT,
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// GISEL: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: // MIs[0] Operand 2
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// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 0,
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def : Pat<
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(TgtCat i32:$src0, 0),
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(CAT0 GPR32:$src0)
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>;
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// GISEL: GIM_CheckOpcode, /*MI*/0, MyTarget::G_TGT_CAT,
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// GISEL: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: // MIs[0] Operand 2
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// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 93,
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def : Pat<
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(TgtCat i32:$src0, 93),
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(CAT1 GPR32:$src0)
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>;
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