forked from OSchip/llvm-project
197 lines
6.5 KiB
TableGen
197 lines
6.5 KiB
TableGen
//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Subtarget Features
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//===----------------------------------------------------------------------===//
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// Debugging Features
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def FeatureDumpCode : SubtargetFeature <"DumpCode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter">;
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def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
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"EnableIRStructurizer",
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"false",
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"Disable IR Structurizer">;
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def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
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"EnablePromoteAlloca",
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"true",
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"Enable promote alloca pass">;
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// Target features
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def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
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"EnableIfCvt",
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"false",
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"Disable the if conversion pass">;
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def FeatureFP64 : SubtargetFeature<"fp64",
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"FP64",
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"true",
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"Enable double precision operations">;
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def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
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"FP64Denormals",
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"true",
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"Enable double precision denormal handling",
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[FeatureFP64]>;
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// Some instructions do not support denormals despite this flag. Using
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// fp32 denormals also causes instructions to run at the double
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// precision rate for the device.
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def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
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"FP32Denormals",
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"true",
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"Enable single precision denormal handling">;
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def Feature64BitPtr : SubtargetFeature<"64BitPtr",
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"Is64bit",
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"true",
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"Specify if 64-bit addressing should be used">;
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def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
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"R600ALUInst",
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"false",
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"Older version of ALU instructions encoding">;
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def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
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"HasVertexCache",
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"true",
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"Specify use of dedicated vertex cache">;
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def FeatureCaymanISA : SubtargetFeature<"caymanISA",
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"CaymanISA",
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"true",
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"Use Cayman ISA">;
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def FeatureCFALUBug : SubtargetFeature<"cfalubug",
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"CFALUBug",
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"true",
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"GPU has CF_ALU bug">;
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// XXX - This should probably be removed once enabled by default
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def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
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"EnableLoadStoreOpt",
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"true",
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"Enable SI load/store optimizer pass">;
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def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
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"FlatAddressSpace",
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"true",
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"Support flat address space">;
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class SubtargetFeatureFetchLimit <string Value> :
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SubtargetFeature <"fetch"#Value,
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"TexVTXClauseSize",
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Value,
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"Limit the maximum number of fetches in a clause to "#Value>;
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def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
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def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
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class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
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"wavefrontsize"#Value,
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"WavefrontSize",
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!cast<string>(Value),
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"The number of threads per wavefront">;
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def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
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def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
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def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
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class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
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"localmemorysize"#Value,
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"LocalMemorySize",
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!cast<string>(Value),
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"The size of local memory in bytes">;
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class SubtargetFeatureGeneration <string Value,
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list<SubtargetFeature> Implies> :
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SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
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Value#" GPU generation", Implies>;
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def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
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def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
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def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
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def FeatureR600 : SubtargetFeatureGeneration<"R600",
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[FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
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def FeatureR700 : SubtargetFeatureGeneration<"R700",
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[FeatureFetchLimit16, FeatureLocalMemorySize0]>;
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def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
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[FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
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def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
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[FeatureFetchLimit16, FeatureWavefrontSize64,
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FeatureLocalMemorySize32768]
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>;
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def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
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FeatureWavefrontSize64]>;
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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
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def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
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//===----------------------------------------------------------------------===//
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def AMDGPUInstrInfo : InstrInfo {
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let guessInstructionProperties = 1;
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}
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def AMDGPUAsmParser : AsmParser {
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// Some of the R600 registers have the same name, so this crashes.
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// For example T0_XYZW and T0_XY both have the asm name T0.
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let ShouldEmitMatchRegisterName = 0;
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}
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def AMDGPU : Target {
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// Pull in Instruction Info:
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let InstructionSet = AMDGPUInstrInfo;
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let AssemblyParsers = [AMDGPUAsmParser];
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}
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// Dummy Instruction itineraries for pseudo instructions
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def ALU_NULL : FuncUnit;
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def NullALU : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Predicate helper class
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//===----------------------------------------------------------------------===//
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class PredicateControl {
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Predicate SubtargetPredicate;
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list<Predicate> OtherPredicates = [];
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list<Predicate> Predicates = !listconcat([SubtargetPredicate],
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OtherPredicates);
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}
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// Include AMDGPU TD files
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include "R600Schedule.td"
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include "SISchedule.td"
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include "Processors.td"
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include "AMDGPUInstrInfo.td"
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include "AMDGPUIntrinsics.td"
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include "AMDGPURegisterInfo.td"
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include "AMDGPUInstructions.td"
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include "AMDGPUCallingConv.td"
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