forked from OSchip/llvm-project
265 lines
12 KiB
C++
265 lines
12 KiB
C++
//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
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#include "AArch64.h"
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#include "AArch64RegisterInfo.h"
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#include "llvm/CodeGen/MachineCombinerPattern.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "AArch64GenInstrInfo.inc"
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namespace llvm {
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class AArch64Subtarget;
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class AArch64TargetMachine;
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class AArch64InstrInfo : public AArch64GenInstrInfo {
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// Reserve bits in the MachineMemOperand target hint flags, starting at 1.
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// They will be shifted into MOTargetHintStart when accessed.
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enum TargetMemOperandFlags {
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MOSuppressPair = 1
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};
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const AArch64RegisterInfo RI;
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const AArch64Subtarget &Subtarget;
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public:
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explicit AArch64InstrInfo(const AArch64Subtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
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unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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bool isAsCheapAsAMove(const MachineInstr *MI) const override;
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bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &DstReg, unsigned &SubIdx) const override;
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bool
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areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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AliasAnalysis *AA = nullptr) const override;
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// Returns true if there is a shiftable register and that the shift value
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/// is non-zero.
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bool hasShiftedReg(const MachineInstr *MI) const;
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/// Returns true if there is an extendable register and that the extending
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/// value is non-zero.
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bool hasExtendedReg(const MachineInstr *MI) const;
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/// \brief Does this instruction set its full destination register to zero?
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bool isGPRZero(const MachineInstr *MI) const;
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/// \brief Does this instruction rename a GPR without modifying bits?
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bool isGPRCopy(const MachineInstr *MI) const;
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/// \brief Does this instruction rename an FPR without modifying bits?
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bool isFPRCopy(const MachineInstr *MI) const;
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/// Return true if this is load/store scales or extends its register offset.
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/// This refers to scaling a dynamic index as opposed to scaled immediates.
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/// MI should be a memory op that allows scaled addressing.
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bool isScaledAddr(const MachineInstr *MI) const;
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/// Return true if pairing the given load or store is hinted to be
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/// unprofitable.
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bool isLdStPairSuppressed(const MachineInstr *MI) const;
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/// Hint that pairing the given load or store is unprofitable.
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void suppressLdStPair(MachineInstr *MI) const;
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bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
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unsigned &Offset,
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const TargetRegisterInfo *TRI) const override;
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bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
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int &Offset, int &Width,
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const TargetRegisterInfo *TRI) const;
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bool enableClusterLoads() const override { return true; }
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bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
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unsigned NumLoads) const override;
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bool shouldScheduleAdjacent(MachineInstr *First,
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MachineInstr *Second) const override;
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MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
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uint64_t Offset, const MDNode *Var,
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const MDNode *Expr, DebugLoc DL) const;
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void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc, unsigned Opcode,
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llvm::ArrayRef<unsigned> Indices) const;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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using TargetInstrInfo::foldMemoryOperandImpl;
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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ArrayRef<unsigned> Ops,
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MachineBasicBlock::iterator InsertPt,
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int FrameIndex) const override;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const override;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
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unsigned, unsigned, int &, int &, int &) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg) const override;
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void getNoopForMachoTarget(MCInst &NopInst) const override;
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/// analyzeCompare - For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
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/// Return true if the comparison instruction can be analyzed.
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bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &CmpMask,
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int &CmpValue) const override;
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/// optimizeCompareInstr - Convert the instruction supplying the argument to
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/// the comparison into one that sets the zero bit in the flags register.
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bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const override;
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bool optimizeCondBranch(MachineInstr *MI) const override;
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/// Return true when there is potentially a faster code sequence
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/// for an instruction chain ending in <Root>. All potential patterns are
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/// listed in the <Patterns> array.
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bool getMachineCombinerPatterns(MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns)
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const override;
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/// When getMachineCombinerPatterns() finds patterns, this function generates
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/// the instructions that could replace the original code sequence
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void genAlternativeCodeSequence(
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MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
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/// useMachineCombiner - AArch64 supports MachineCombiner
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bool useMachineCombiner() const override;
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableBitmaskMachineOperandTargetFlags() const override;
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private:
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void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
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MachineBasicBlock *TBB,
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ArrayRef<MachineOperand> Cond) const;
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};
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/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
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/// plus Offset. This is intended to be used from within the prolog/epilog
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/// insertion (PEI) pass, where a virtual scratch register may be allocated
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/// if necessary, to be replaced by the scavenger at the end of PEI.
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void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
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const TargetInstrInfo *TII,
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MachineInstr::MIFlag = MachineInstr::NoFlags,
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bool SetNZCV = false);
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/// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
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/// FP. Return false if the offset could not be handled directly in MI, and
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/// return the left-over portion by reference.
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bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const AArch64InstrInfo *TII);
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/// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
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enum AArch64FrameOffsetStatus {
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AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
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AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
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AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
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};
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/// \brief Check if the @p Offset is a valid frame offset for @p MI.
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/// The returned value reports the validity of the frame offset for @p MI.
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/// It uses the values defined by AArch64FrameOffsetStatus for that.
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/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
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/// use an offset.eq
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/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
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/// rewriten in @p MI.
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/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
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/// amount that is off the limit of the legal offset.
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/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
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/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
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/// If set, @p EmittableOffset contains the amount that can be set in @p MI
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/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
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/// is a legal offset.
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int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
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bool *OutUseUnscaledOp = nullptr,
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unsigned *OutUnscaledOp = nullptr,
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int *EmittableOffset = nullptr);
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static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
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static inline bool isCondBranchOpcode(int Opc) {
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switch (Opc) {
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case AArch64::Bcc:
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case AArch64::CBZW:
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case AArch64::CBZX:
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case AArch64::CBNZW:
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case AArch64::CBNZX:
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case AArch64::TBZW:
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case AArch64::TBZX:
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case AArch64::TBNZW:
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case AArch64::TBNZX:
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return true;
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default:
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return false;
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}
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}
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static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
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} // end namespace llvm
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#endif
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