forked from OSchip/llvm-project
163 lines
6.3 KiB
TableGen
163 lines
6.3 KiB
TableGen
//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// AArch64 Subtarget features.
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//
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
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"Enable ARMv8 FP">;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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"Enable cryptographic instructions">;
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
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"Enable ARMv8 CRC-32 checksum instructions">;
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def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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"Enable ARMv8 PMUv3 Performance Monitors extension">;
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/// Cyclone has register move instructions which are "free".
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def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
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"Has zero-cycle register moves">;
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/// Cyclone has instructions which zero registers for "free".
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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def FeatureStrictAlign : SubtargetFeature<"strict-align",
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"StrictAlign", "true",
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"Disallow all unaligned memory "
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"access">;
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def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
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"Reserve X18, making it unavailable "
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"as a GPR">;
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//===----------------------------------------------------------------------===//
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// Architectures.
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//
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def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
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"Support ARM v8.1a instructions", [FeatureCRC]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "AArch64RegisterInfo.td"
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include "AArch64CallingConvention.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "AArch64Schedule.td"
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include "AArch64InstrInfo.td"
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def AArch64InstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// AArch64 Processors supported.
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//
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include "AArch64SchedA53.td"
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include "AArch64SchedA57.td"
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include "AArch64SchedCyclone.td"
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors",
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[FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto,
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FeatureCRC,
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FeaturePerfMon]>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors",
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[FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto,
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FeatureCRC,
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FeaturePerfMon]>;
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def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
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"Cyclone",
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[FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto,
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FeatureCRC,
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FeaturePerfMon,
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FeatureZCRegMove, FeatureZCZeroing]>;
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def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
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FeatureNEON,
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FeatureCRC,
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FeaturePerfMon]>;
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def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
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def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
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// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
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def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
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def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
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//===----------------------------------------------------------------------===//
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// Assembly parser
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//===----------------------------------------------------------------------===//
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def GenericAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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string Name = "generic";
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}
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def AppleAsmParserVariant : AsmParserVariant {
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int Variant = 1;
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string Name = "apple-neon";
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}
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//===----------------------------------------------------------------------===//
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// Assembly printer
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//===----------------------------------------------------------------------===//
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// AArch64 Uses the MC printer for asm output, so make sure the TableGen
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// AsmWriter bits get associated with the correct class.
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def GenericAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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bit isMCAsmWriter = 1;
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}
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def AppleAsmWriter : AsmWriter {
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let AsmWriterClassName = "AppleInstPrinter";
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int PassSubtarget = 1;
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int Variant = 1;
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int isMCAsmWriter = 1;
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}
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//===----------------------------------------------------------------------===//
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// Target Declaration
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//===----------------------------------------------------------------------===//
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def AArch64 : Target {
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let InstructionSet = AArch64InstrInfo;
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let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
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let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
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}
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