forked from OSchip/llvm-project
177 lines
10 KiB
LLVM
177 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck --check-prefixes=AVX2,AVX2-SLOW %s
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+fast-variable-shuffle | FileCheck --check-prefixes=AVX2,AVX2-FAST %s
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; These patterns are produced by LoopVectorizer for interleaved loads.
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define void @vf2(<6 x i16>* %in.vec, <2 x i16>* %out.vec0, <2 x i16>* %out.vec1, <2 x i16>* %out.vec2) nounwind {
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; AVX2-SLOW-LABEL: vf2:
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; AVX2-SLOW: # %bb.0:
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; AVX2-SLOW-NEXT: vmovdqa (%rdi), %xmm0
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; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm1 = xmm0[0,3,2,3,4,5,6,7]
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; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[0,2,2,3]
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; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm2 = xmm2[1,2,2,3,4,5,6,7]
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; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
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; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[2,1,2,3,4,5,6,7]
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; AVX2-SLOW-NEXT: vmovd %xmm1, (%rsi)
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; AVX2-SLOW-NEXT: vmovd %xmm2, (%rdx)
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; AVX2-SLOW-NEXT: vmovd %xmm0, (%rcx)
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; AVX2-SLOW-NEXT: retq
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;
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; AVX2-FAST-LABEL: vf2:
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; AVX2-FAST: # %bb.0:
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; AVX2-FAST-NEXT: vmovdqa (%rdi), %xmm0
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; AVX2-FAST-NEXT: vpshuflw {{.*#+}} xmm1 = xmm0[0,3,2,3,4,5,6,7]
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; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm2 = xmm0[2,3,8,9,u,u,u,u,u,u,u,u,u,u,u,u]
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; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,10,11,u,u,u,u,u,u,u,u,u,u,u,u]
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; AVX2-FAST-NEXT: vmovd %xmm1, (%rsi)
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; AVX2-FAST-NEXT: vmovd %xmm2, (%rdx)
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; AVX2-FAST-NEXT: vmovd %xmm0, (%rcx)
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; AVX2-FAST-NEXT: retq
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%wide.vec = load <6 x i16>, <6 x i16>* %in.vec, align 32
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%strided.vec0 = shufflevector <6 x i16> %wide.vec, <6 x i16> poison, <2 x i32> <i32 0, i32 3>
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%strided.vec1 = shufflevector <6 x i16> %wide.vec, <6 x i16> poison, <2 x i32> <i32 1, i32 4>
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%strided.vec2 = shufflevector <6 x i16> %wide.vec, <6 x i16> poison, <2 x i32> <i32 2, i32 5>
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store <2 x i16> %strided.vec0, <2 x i16>* %out.vec0, align 32
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store <2 x i16> %strided.vec1, <2 x i16>* %out.vec1, align 32
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store <2 x i16> %strided.vec2, <2 x i16>* %out.vec2, align 32
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ret void
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}
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define void @vf4(<12 x i16>* %in.vec, <4 x i16>* %out.vec0, <4 x i16>* %out.vec1, <4 x i16>* %out.vec2) nounwind {
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; AVX2-SLOW-LABEL: vf4:
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; AVX2-SLOW: # %bb.0:
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; AVX2-SLOW-NEXT: vmovdqa (%rdi), %xmm0
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; AVX2-SLOW-NEXT: vmovdqa 16(%rdi), %xmm1
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; AVX2-SLOW-NEXT: vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
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; AVX2-SLOW-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,6,7,12,13,2,3,u,u,u,u,u,u,u,u]
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; AVX2-SLOW-NEXT: vpblendd {{.*#+}} xmm3 = xmm0[0],xmm1[1],xmm0[2,3]
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; AVX2-SLOW-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[2,3,8,9,14,15,4,5,u,u,u,u,u,u,u,u]
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; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,3,2,3,4,5,6,7]
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; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
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; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[2,1,2,3,4,5,6,7]
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; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; AVX2-SLOW-NEXT: vmovq %xmm2, (%rsi)
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; AVX2-SLOW-NEXT: vmovq %xmm3, (%rdx)
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; AVX2-SLOW-NEXT: vmovq %xmm0, (%rcx)
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; AVX2-SLOW-NEXT: retq
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;
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; AVX2-FAST-LABEL: vf4:
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; AVX2-FAST: # %bb.0:
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; AVX2-FAST-NEXT: vmovdqa (%rdi), %xmm0
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; AVX2-FAST-NEXT: vmovdqa 16(%rdi), %xmm1
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; AVX2-FAST-NEXT: vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
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; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,6,7,12,13,2,3,u,u,u,u,u,u,u,u]
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; AVX2-FAST-NEXT: vpblendd {{.*#+}} xmm3 = xmm0[0],xmm1[1],xmm0[2,3]
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; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[2,3,8,9,14,15,4,5,u,u,u,u,u,u,u,u]
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; AVX2-FAST-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,3,2,3,4,5,6,7]
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; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,10,11,u,u,u,u,u,u,u,u,u,u,u,u]
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; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; AVX2-FAST-NEXT: vmovq %xmm2, (%rsi)
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; AVX2-FAST-NEXT: vmovq %xmm3, (%rdx)
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; AVX2-FAST-NEXT: vmovq %xmm0, (%rcx)
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; AVX2-FAST-NEXT: retq
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%wide.vec = load <12 x i16>, <12 x i16>* %in.vec, align 32
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%strided.vec0 = shufflevector <12 x i16> %wide.vec, <12 x i16> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
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%strided.vec1 = shufflevector <12 x i16> %wide.vec, <12 x i16> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
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%strided.vec2 = shufflevector <12 x i16> %wide.vec, <12 x i16> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
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store <4 x i16> %strided.vec0, <4 x i16>* %out.vec0, align 32
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store <4 x i16> %strided.vec1, <4 x i16>* %out.vec1, align 32
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store <4 x i16> %strided.vec2, <4 x i16>* %out.vec2, align 32
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ret void
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}
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define void @vf8(<24 x i16>* %in.vec, <8 x i16>* %out.vec0, <8 x i16>* %out.vec1, <8 x i16>* %out.vec2) nounwind {
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; AVX2-LABEL: vf8:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vmovdqa (%rdi), %xmm0
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; AVX2-NEXT: vmovdqa 16(%rdi), %xmm1
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; AVX2-NEXT: vmovdqa 32(%rdi), %xmm2
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; AVX2-NEXT: vpblendw {{.*#+}} xmm3 = xmm0[0,1],xmm2[2],xmm0[3,4],xmm2[5],xmm0[6,7]
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; AVX2-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm1[1],xmm3[2,3],xmm1[4],xmm3[5,6],xmm1[7]
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; AVX2-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[0,1,6,7,12,13,2,3,8,9,14,15,4,5,10,11]
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; AVX2-NEXT: vpblendw {{.*#+}} xmm4 = xmm2[0],xmm0[1,2],xmm2[3],xmm0[4,5],xmm2[6],xmm0[7]
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; AVX2-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1],xmm1[2],xmm4[3,4],xmm1[5],xmm4[6,7]
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; AVX2-NEXT: vpshufb {{.*#+}} xmm4 = xmm4[2,3,8,9,14,15,4,5,10,11,0,1,6,7,12,13]
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; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3],xmm2[4],xmm0[5,6],xmm2[7]
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; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3],xmm0[4,5],xmm1[6],xmm0[7]
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; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,10,11,0,1,6,7,12,13,2,3,8,9,14,15]
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; AVX2-NEXT: vmovdqa %xmm3, (%rsi)
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; AVX2-NEXT: vmovdqa %xmm4, (%rdx)
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; AVX2-NEXT: vmovdqa %xmm0, (%rcx)
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; AVX2-NEXT: retq
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%wide.vec = load <24 x i16>, <24 x i16>* %in.vec, align 32
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%strided.vec0 = shufflevector <24 x i16> %wide.vec, <24 x i16> poison, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
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%strided.vec1 = shufflevector <24 x i16> %wide.vec, <24 x i16> poison, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
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%strided.vec2 = shufflevector <24 x i16> %wide.vec, <24 x i16> poison, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
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store <8 x i16> %strided.vec0, <8 x i16>* %out.vec0, align 32
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store <8 x i16> %strided.vec1, <8 x i16>* %out.vec1, align 32
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store <8 x i16> %strided.vec2, <8 x i16>* %out.vec2, align 32
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ret void
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}
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define void @vf16(<48 x i16>* %in.vec, <16 x i16>* %out.vec0, <16 x i16>* %out.vec1, <16 x i16>* %out.vec2) nounwind {
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; AVX2-LABEL: vf16:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vmovdqa (%rdi), %ymm0
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; AVX2-NEXT: vmovdqa 32(%rdi), %ymm1
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = <255,255,u,u,0,0,255,255,u,u,0,0,255,255,u,u,0,0,255,255,u,u,0,0,255,255,u,u,0,0,255,255>
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; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm2
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; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm2[2,3,0,1]
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; AVX2-NEXT: vpblendw {{.*#+}} ymm2 = ymm2[0],ymm3[1],ymm2[2,3],ymm3[4],ymm2[5,6],ymm3[7],ymm2[8],ymm3[9],ymm2[10,11],ymm3[12],ymm2[13,14],ymm3[15]
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; AVX2-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[0,1,6,7,12,13,2,3,4,5,14,15,8,9,10,11,16,17,22,23,28,29,18,19,20,21,30,31,24,25,26,27]
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; AVX2-NEXT: vmovdqa 80(%rdi), %xmm3
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; AVX2-NEXT: vmovdqa 64(%rdi), %xmm4
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; AVX2-NEXT: vpblendw {{.*#+}} xmm5 = xmm4[0,1],xmm3[2],xmm4[3,4],xmm3[5],xmm4[6,7]
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; AVX2-NEXT: vpshufb {{.*#+}} xmm5 = xmm5[u,u,u,u,u,u,2,3,8,9,14,15,4,5,10,11]
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; AVX2-NEXT: vinserti128 $1, %xmm5, %ymm0, %ymm5
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; AVX2-NEXT: vpblendw {{.*#+}} ymm5 = ymm2[0,1,2],ymm5[3,4,5,6,7],ymm2[8,9,10],ymm5[11,12,13,14,15]
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; AVX2-NEXT: vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,6,5,4,7]
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; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm5[4,5,6,7]
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm5 = <255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255>
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; AVX2-NEXT: vpblendvb %ymm5, %ymm1, %ymm0, %ymm5
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; AVX2-NEXT: vpermq {{.*#+}} ymm6 = ymm5[2,3,0,1]
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; AVX2-NEXT: vpblendw {{.*#+}} ymm5 = ymm5[0,1],ymm6[2],ymm5[3,4],ymm6[5],ymm5[6,7,8,9],ymm6[10],ymm5[11,12],ymm6[13],ymm5[14,15]
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; AVX2-NEXT: vpshufb {{.*#+}} ymm5 = ymm5[2,3,8,9,14,15,4,5,12,13,10,11,0,1,6,7,18,19,24,25,30,31,20,21,28,29,26,27,16,17,22,23]
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; AVX2-NEXT: vpblendw {{.*#+}} xmm6 = xmm3[0,1],xmm4[2],xmm3[3,4],xmm4[5],xmm3[6,7]
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; AVX2-NEXT: vpshufb {{.*#+}} xmm6 = xmm6[u,u,u,u,u,u,4,5,10,11,0,1,6,7,12,13]
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; AVX2-NEXT: vinserti128 $1, %xmm6, %ymm0, %ymm6
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; AVX2-NEXT: vpblendw {{.*#+}} ymm6 = ymm5[0,1,2],ymm6[3,4,5,6,7],ymm5[8,9,10],ymm6[11,12,13,14,15]
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; AVX2-NEXT: vpshufhw {{.*#+}} xmm5 = xmm5[0,1,2,3,5,6,7,4]
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; AVX2-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0,1,2,3],ymm6[4,5,6,7]
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm6 = <u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u,255,255,0,0,u,u>
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; AVX2-NEXT: vpblendvb %ymm6, %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1,2],ymm1[3],ymm0[4,5],ymm1[6],ymm0[7],ymm1[8],ymm0[9,10],ymm1[11],ymm0[12,13],ymm1[14],ymm0[15]
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; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[4,5,10,11,0,1,6,7,12,13,2,3,8,9,14,15,20,21,26,27,u,u,u,u,u,u,u,u,u,u,u,u]
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; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm4[0],xmm3[1],xmm4[2,3],xmm3[4],xmm4[5,6],xmm3[7]
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; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u,u,u,u,0,1,6,7,12,13,2,3,8,9,14,15]
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; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1
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; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm1[5,6,7]
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; AVX2-NEXT: vmovdqa %ymm2, (%rsi)
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; AVX2-NEXT: vmovdqa %ymm5, (%rdx)
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; AVX2-NEXT: vmovdqa %ymm0, (%rcx)
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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%wide.vec = load <48 x i16>, <48 x i16>* %in.vec, align 32
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%strided.vec0 = shufflevector <48 x i16> %wide.vec, <48 x i16> poison, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
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%strided.vec1 = shufflevector <48 x i16> %wide.vec, <48 x i16> poison, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
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%strided.vec2 = shufflevector <48 x i16> %wide.vec, <48 x i16> poison, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
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store <16 x i16> %strided.vec0, <16 x i16>* %out.vec0, align 32
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store <16 x i16> %strided.vec1, <16 x i16>* %out.vec1, align 32
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store <16 x i16> %strided.vec2, <16 x i16>* %out.vec2, align 32
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ret void
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}
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