..
AsmParser
[RISCV] Change parseVTypeI function
2021-02-12 19:38:34 +08:00
Disassembler
[RISCV] Fix shared libs build
2021-02-09 06:14:25 -06:00
MCTargetDesc
[RISCV] Make scalable vector FMA commutable for register allocation.
2021-02-08 10:05:33 -08:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
CMakeLists.txt
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCV.h
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCV.td
[RISCV] Fix name of Zba extension (NFC)
2021-01-24 21:02:34 +00:00
RISCVAsmPrinter.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVCallLowering.cpp
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCallLowering.h
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCallingConv.td
…
RISCVCleanupVSETVLI.cpp
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
RISCVFrameLowering.cpp
[RISCV] Simplify BP initialisation
2021-02-17 20:33:20 +08:00
RISCVFrameLowering.h
[RISCV] Frame handling for RISC-V V extension.
2021-02-17 14:05:19 +08:00
RISCVISelDAGToDAG.cpp
[RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.
2021-02-19 10:07:12 -08:00
RISCVISelDAGToDAG.h
[RISCV] Split zvlsseg searchable table into 4 separate tables. Index by properties rather than intrinsic ID.
2021-02-18 19:00:49 -08:00
RISCVISelLowering.cpp
[RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64
2021-02-19 10:07:12 -08:00
RISCVISelLowering.h
[RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64
2021-02-19 10:07:12 -08:00
RISCVInstrFormats.td
[RISCV] Make scalable vector FMA commutable for register allocation.
2021-02-08 10:05:33 -08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp
[RISCV] Spilling for RISC-V V extension. (2nd version)
2021-02-17 14:05:19 +08:00
RISCVInstrInfo.h
[RISCV] Frame handling for RISC-V V extension.
2021-02-17 14:05:19 +08:00
RISCVInstrInfo.td
[RISCV] Add expicit i32/i64 types to RV32 or RV64 only isel patterns. NFC
2021-02-15 14:36:05 -08:00
RISCVInstrInfoA.td
[RISCV] Rename the RVVBaseAddr ComplexPattern to just BaseAddr and use it to merge some scalar load/store patterns too.
2021-02-13 12:01:51 -08:00
RISCVInstrInfoB.td
[RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64
2021-02-19 10:07:12 -08:00
RISCVInstrInfoC.td
[RISCV] More whitespace and comment typo fixes in RISCVInstrInfoC.td
2021-02-11 02:32:36 +00:00
RISCVInstrInfoD.td
[RISCV] Add expicit i32/i64 types to RV32 or RV64 only isel patterns. NFC
2021-02-15 14:36:05 -08:00
RISCVInstrInfoF.td
[RISCV] Add expicit i32/i64 types to RV32 or RV64 only isel patterns. NFC
2021-02-15 14:36:05 -08:00
RISCVInstrInfoM.td
[RISCV] Don't remove (and X, 0xffffffff) from inputs when matching RISCVISD::DIVUW/REMUW to 64-bit DIVU/REMU.
2020-11-26 23:15:41 -08:00
RISCVInstrInfoV.td
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Prune unneeded indexed load/store pseudo instructions.
2021-02-18 23:08:39 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Fix typo. Use ValueType instead of LLVMType.
2021-02-18 23:21:27 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add support for fixed vector MULHU/MULHS.
2021-02-18 09:15:08 -08:00
RISCVInstrInfoZfh.td
[RISCV] Add expicit i32/i64 types to RV32 or RV64 only isel patterns. NFC
2021-02-15 14:36:05 -08:00
RISCVInstructionSelector.cpp
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
RISCVMachineFunctionInfo.h
[RISCV] Frame handling for RISC-V V extension.
2021-02-17 14:05:19 +08:00
RISCVMergeBaseOffset.cpp
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Frame handling for RISC-V V extension.
2021-02-17 14:05:19 +08:00
RISCVRegisterInfo.h
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RISCVRegisterInfo.td
[RISCV] Use XLenRI alias for RegInfoByHwMode instances
2021-02-18 19:38:36 +00:00
RISCVSchedRocket.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSchedSiFive7.td
[RISCV] Use the commercial name for scheduling model (NFC)
2020-10-23 16:33:27 -05:00
RISCVSchedule.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp
[RISCV] Add support loads, stores, and splats of vXi1 fixed vectors.
2021-02-11 09:13:16 -08:00
RISCVSubtarget.h
[RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other.
2021-02-09 10:47:23 -08:00
RISCVSystemOperands.td
[RISCV] Enable the use of the old mucounteren name
2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCVTargetMachine.h
[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other.
2021-02-09 10:47:23 -08:00
RISCVTargetTransformInfo.h
[RISCV] Initial support of LoopVectorizer for RISC-V Vector.
2021-02-09 06:32:18 +08:00
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