forked from OSchip/llvm-project
d2d0f46cd2
This patch adds a simple Cortex-M4 schedule, renaming the existing M3 schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM: https://developer.arm.com/docs/ddi0439/latest Most of these are 1, with the important exception being loads taking 2 cycles. A few others are also higher, but I don't believe they make a large difference. I've repurposed the M3 schedule as the latencies are mostly the same between the two cores, with the M4 having more FP and DSP instructions. We also turn on MISched and UseAA for the cores that now use this. It also adds some schedule Write's to various instruction to make things simpler. Differential Revision: https://reviews.llvm.org/D54142 llvm-svn: 360768 |
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| .. | ||
| aliasing.ll | ||
| multi-use-loads.ll | ||
| smlad0.ll | ||
| smlad1.ll | ||
| smlad2.ll | ||
| smlad3.ll | ||
| smlad4.ll | ||
| smlad5.ll | ||
| smlad8.ll | ||
| smlad9.ll | ||
| smlad10.ll | ||
| smlad11.ll | ||
| smlad12.ll | ||
| smladx-1.ll | ||
| smlald0.ll | ||
| smlald1.ll | ||
| smlald2.ll | ||
| smlaldx-1.ll | ||
| smlaldx-2.ll | ||
| unroll-n-jam-smlad.ll | ||