forked from OSchip/llvm-project
156 lines
6.1 KiB
LLVM
156 lines
6.1 KiB
LLVM
;; Test to ensure that we are not using any of the aliased reserved registers
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;; under the Extended Altivec ABI on AIX.
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+altivec \
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; RUN: -stop-after=machine-cp -mtriple powerpc64-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefix=DFLABI
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+altivec -vec-extabi\
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; RUN: -stop-after=machine-cp -mtriple powerpc64-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefix=EXTABI
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define double @dbl_test(double %a, double* %b) local_unnamed_addr {
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entry:
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%0 = load volatile double, double* %b, align 4
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%add = fadd double %0, %a
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store volatile double %add, double* %b, align 4
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;; Clobbered all vector and floating point registers. In the default Altivec
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;; ABI this forces a register spill since no registers are free to use.
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tail call void asm sideeffect "nop", "~{v19},~{v18},~{v17},~{v16},~{v15},~{v14},~{v13},~{v12},~{v11},~{v10},~{v9},~{v8},~{v7},~{v6},~{v5},~{v4},~{v3},~{v2},~{v1},~{v0},~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
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%mul = fmul double %a, %a
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%1 = load volatile double, double* %b, align 4
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%add1 = fadd double %mul, %1
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store volatile double %add1, double* %b, align 4
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%2 = load volatile double, double* %b, align 4
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ret double %2
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}
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define <4 x i32> @vec_test(<4 x i32> %a, <4 x i32>* %b) local_unnamed_addr {
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entry:
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%0 = load volatile <4 x i32>, <4 x i32>* %b, align 4
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%add = add <4 x i32> %0, %a
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store volatile <4 x i32> %add, <4 x i32>* %b, align 4
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tail call void asm sideeffect "nop", "~{v19},~{v18},~{v17},~{v16},~{v15},~{v14},~{v13},~{v12},~{v11},~{v10},~{v9},~{v8},~{v7},~{v6},~{v5},~{v4},~{v3},~{v2},~{v1},~{v0},~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
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%mul = mul <4 x i32> %a, %a
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%1 = load volatile <4 x i32>, <4 x i32>* %b, align 4
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%add1 = add <4 x i32> %mul, %1
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store volatile <4 x i32> %add1, <4 x i32>* %b, align 4
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%2 = load volatile <4 x i32>, <4 x i32>* %b, align 4
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ret <4 x i32> %2
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}
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; DFLABI-LABEL: dbl_test
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; DFLABI-NOT: $v20
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; DFLABI-NOT: $v21
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; DFLABI-NOT: $v22
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; DFLABI-NOT: $v23
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; DFLABI-NOT: $v24
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; DFLABI-NOT: $v25
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; DFLABI-NOT: $v26
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; DFLABI-NOT: $v27
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; DFLABI-NOT: $v28
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; DFLABI-NOT: $v29
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; DFLABI-NOT: $v30
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; DFLABI-NOT: $v31
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; DFLABI-NOT: $vf20
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; DFLABI-NOT: $vf21
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; DFLABI-NOT: $vf22
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; DFLABI-NOT: $vf23
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; DFLABI-NOT: $vf24
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; DFLABI-NOT: $vf25
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; DFLABI-NOT: $vf26
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; DFLABI-NOT: $vf27
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; DFLABI-NOT: $vf28
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; DFLABI-NOT: $vf29
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; DFLABI-NOT: $vf30
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; DFLABI-NOT: $vf31
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; DFLABI-NOT: $vs20
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; DFLABI-NOT: $vs21
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; DFLABI-NOT: $vs22
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; DFLABI-NOT: $vs23
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; DFLABI-NOT: $vs24
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; DFLABI-NOT: $vs25
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; DFLABI-NOT: $vs26
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; DFLABI-NOT: $vs27
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; DFLABI-NOT: $vs28
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; DFLABI-NOT: $vs29
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; DFLABI-NOT: $vs30
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; DFLABI-NOT: $vs31
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; EXTABI-LABEL: vec_test
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; EXTABI: liveins:
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; EXTABI-NEXT: - { reg: '$f1', virtual-reg: '' }
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; EXTABI-NEXT: - { reg: '$x4', virtual-reg: '' }
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; EXTABI: body: |
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; EXTABI: bb.0.entry:
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; EXTABI: liveins: $f1, $x4
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; EXTABI-DAG: renamable $f0 = XFLOADf64 $zero8, renamable $x4 :: (volatile load 8 from %ir.b, align 4)
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; EXTABI-DAG: renamable $f0 = nofpexcept XSADDDP killed renamable $f0, renamable $f1, implicit $rm
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; EXTABI-DAG: renamable $vf31 = nofpexcept XSMULDP killed renamable $f1, renamable $f1, implicit $rm
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; EXTABI: XFSTOREf64 killed renamable $f0, $zero8, renamable $x4 :: (volatile store 8 into %ir.b, align 4)
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; EXTABI-LABEL: INLINEASM
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; EXTABI-DAG: renamable $f0 = XFLOADf64 $zero8, renamable $x4 :: (volatile load 8 from %ir.b, align 4)
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; EXTABI-DAG: renamable $f0 = nofpexcept XSADDDP killed renamable $vf31, killed renamable $f0, implicit $rm
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; EXTABI-DAG: XFSTOREf64 killed renamable $f0, $zero8, renamable $x4 :: (volatile store 8 into %ir.b, align 4)
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; EXTABI: renamable $f1 = XFLOADf64 $zero8, killed renamable $x4 :: (volatile load 8 from %ir.b, align 4)
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; DFLABI-LABEL: vec_test
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; DFLABI-NOT: $v20
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; DFLABI-NOT: $v21
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; DFLABI-NOT: $v22
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; DFLABI-NOT: $v23
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; DFLABI-NOT: $v24
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; DFLABI-NOT: $v25
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; DFLABI-NOT: $v26
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; DFLABI-NOT: $v27
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; DFLABI-NOT: $v28
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; DFLABI-NOT: $v29
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; DFLABI-NOT: $v30
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; DFLABI-NOT: $v31
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; DFLABI-NOT: $vf20
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; DFLABI-NOT: $vf21
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; DFLABI-NOT: $vf22
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; DFLABI-NOT: $vf23
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; DFLABI-NOT: $vf24
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; DFLABI-NOT: $vf25
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; DFLABI-NOT: $vf26
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; DFLABI-NOT: $vf27
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; DFLABI-NOT: $vf28
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; DFLABI-NOT: $vf29
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; DFLABI-NOT: $vf30
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; DFLABI-NOT: $vf31
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; DFLABI-NOT: $vs20
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; DFLABI-NOT: $vs21
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; DFLABI-NOT: $vs22
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; DFLABI-NOT: $vs23
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; DFLABI-NOT: $vs24
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; DFLABI-NOT: $vs25
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; DFLABI-NOT: $vs26
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; DFLABI-NOT: $vs27
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; DFLABI-NOT: $vs28
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; DFLABI-NOT: $vs29
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; DFLABI-NOT: $vs30
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; DFLABI-NOT: $vs31
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; EXTABI-LABEL: vec_test
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; EXTABI: liveins:
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; EXTABI-NEXT: - { reg: '$v2', virtual-reg: '' }
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; EXTABI-NEXT: - { reg: '$x3', virtual-reg: '' }
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; EXTABI: body: |
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; EXTABI-DAG: bb.0.entry:
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; EXTABI-DAG: liveins: $v2, $x3
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; EXTABI-DAG: renamable $v3 = LXVW4X $zero8, renamable $x3 :: (volatile load 16 from %ir.b, align 4)
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; EXTABI-DAG: renamable $v31 = COPY $v2
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; EXTABI-DAG: renamable $v2 = VADDUWM killed renamable $v3, $v2
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; EXTABI-LABEL: INLINEASM
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; EXTABI-DAG: renamable $v2 = LXVW4X $zero8, renamable $x3 :: (volatile load 16 from %ir.b, align 4)
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; EXTABI-DAG: renamable $v3 = VMULUWM killed renamable $v31, renamable $v31
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; EXTABI-DAG: renamable $v2 = VADDUWM killed renamable $v3, killed renamable $v2
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; EXTABI-DAG: STXVW4X killed renamable $v2, $zero8, renamable $x3 :: (volatile store 16 into %ir.b, align 4)
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; EXTABI: renamable $v2 = LXVW4X $zero8, killed renamable $x3 :: (volatile load 16 from %ir.b, align 4)
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