forked from OSchip/llvm-project
68 lines
2.3 KiB
LLVM
68 lines
2.3 KiB
LLVM
; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
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; Test that the code that changes the dependences does not allow
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; a load with a negative offset to be overlapped with the post
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; increment store that generates the base register.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: = mem{{u?}}b([[REG:(r[0-9])+]]+#-1)
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; CHECK-NOT: memb([[REG]]{{\+?}}#0) =
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; CHECK: }
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; CHECK: }{{[ \t]*}}:endloop0
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@g0 = external global [1000000 x i8], align 8
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; Function Attrs: nounwind
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define void @f0(i32 %a0, [1000 x i8]* %a1, [1000 x i8]* %a2) #0 {
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b0:
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br i1 undef, label %b1, label %b7
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b1: ; preds = %b0
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br i1 undef, label %b2, label %b6
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b2: ; preds = %b5, %b1
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br i1 undef, label %b3, label %b5
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b3: ; preds = %b3, %b2
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%v0 = phi i32 [ %v17, %b3 ], [ 1, %b2 ]
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%v1 = phi i32 [ %v16, %b3 ], [ 0, %b2 ]
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%v2 = add nsw i32 %v0, -1
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%v3 = getelementptr inbounds [1000 x i8], [1000 x i8]* %a1, i32 undef, i32 %v2
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%v4 = load i8, i8* %v3, align 1, !tbaa !0
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%v5 = zext i8 %v4 to i32
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%v6 = getelementptr inbounds [1000000 x i8], [1000000 x i8]* @g0, i32 0, i32 %v1
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%v7 = load i8, i8* %v6, align 1, !tbaa !0
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%v8 = sext i8 %v7 to i32
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%v9 = getelementptr inbounds [1000 x i8], [1000 x i8]* %a2, i32 undef, i32 %v0
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%v10 = load i8, i8* %v9, align 1, !tbaa !0
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%v11 = sext i8 %v10 to i32
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%v12 = mul nsw i32 %v11, %v8
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%v13 = add nsw i32 %v12, %v5
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%v14 = trunc i32 %v13 to i8
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%v15 = getelementptr inbounds [1000 x i8], [1000 x i8]* %a1, i32 undef, i32 %v0
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store i8 %v14, i8* %v15, align 1, !tbaa !0
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%v16 = add nsw i32 %v1, 1
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%v17 = add nsw i32 %v0, 1
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%v18 = icmp eq i32 %v17, %a0
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br i1 %v18, label %b4, label %b3
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b4: ; preds = %b3
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br label %b5
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b5: ; preds = %b4, %b2
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br i1 undef, label %b6, label %b2
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b6: ; preds = %b5, %b1
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unreachable
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b7: ; preds = %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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