forked from OSchip/llvm-project
37 lines
937 B
LLVM
37 lines
937 B
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that we generate new value jump.
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; CHECK: if (cmp.eq(r{{[0-9]+}}.new,#0)) jump{{.}}
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@g0 = global i32 0, align 4
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@g1 = global i32 10, align 4
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define i32 @f0(i32 %a0) #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = alloca i32, align 4
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%v2 = load i32, i32* @g0, align 4
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store i32 %v2, i32* %v0, align 4
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call void @f2(i32 1, i32 2)
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%v3 = load i32, i32* @g1, align 4
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%v4 = icmp ne i32 %v3, 0
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br i1 %v4, label %b1, label %b2
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b1: ; preds = %b0
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call void @f3(i32 1, i32 2)
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br label %b3
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b2: ; preds = %b0
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call void @f1(i32 10, i32 20)
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br label %b3
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b3: ; preds = %b2, %b1
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ret i32 0
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}
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declare void @f1(i32, i32) #0
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declare void @f2(i32, i32) #0
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declare void @f3(i32, i32) #0
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }
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