forked from OSchip/llvm-project
98 lines
3.4 KiB
LLVM
98 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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define <4 x i1> @t0_all_tautological(<4 x i32> %X) nounwind {
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; CHECK-LABEL: t0_all_tautological:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: adrp x8, .LCPI0_1
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_1]
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: cmeq v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 1, i32 1, i32 2, i32 2>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i1> %cmp
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}
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define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
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; CHECK-LABEL: t1_all_odd_eq:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: dup v2.4s, w8
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; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: movi d1, #0xffff0000ffff0000
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; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
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ret <4 x i1> %cmp
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}
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define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
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; CHECK-LABEL: t1_all_odd_ne:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI2_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: dup v2.4s, w8
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; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: movi d1, #0xffff0000ffff0000
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; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
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%cmp = icmp ne <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
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ret <4 x i1> %cmp
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}
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define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
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; CHECK-LABEL: t2_narrow:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI3_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: dup v2.8h, w8
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; CHECK-NEXT: mul v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: xtn v0.8b, v0.8h
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; CHECK-NEXT: movi d1, #0xffff0000ffff0000
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; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%urem = urem <8 x i16> %X, <i16 3, i16 1, i16 1, i16 9, i16 3, i16 1, i16 1, i16 9>
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%cmp = icmp eq <8 x i16> %urem, <i16 0, i16 0, i16 42, i16 42, i16 0, i16 0, i16 42, i16 42>
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ret <8 x i1> %cmp
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}
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define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
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; CHECK-LABEL: t3_wide:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x9, #-6148914691236517206
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; CHECK-NEXT: adrp x11, .LCPI4_0
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; CHECK-NEXT: mov x8, v0.d[1]
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; CHECK-NEXT: movk x9, #43691
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; CHECK-NEXT: fmov x10, d0
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; CHECK-NEXT: ldr q0, [x11, :lo12:.LCPI4_0]
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; CHECK-NEXT: mul x10, x10, x9
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; CHECK-NEXT: mul x8, x8, x9
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; CHECK-NEXT: fmov d1, x10
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; CHECK-NEXT: mov v1.d[1], x8
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; CHECK-NEXT: cmhs v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: movi d1, #0xffffffff00000000
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; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%urem = urem <2 x i64> %X, <i64 3, i64 1>
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%cmp = icmp eq <2 x i64> %urem, <i64 0, i64 42>
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ret <2 x i1> %cmp
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}
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