forked from OSchip/llvm-project
90 lines
3.4 KiB
LLVM
90 lines
3.4 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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; Integer vector select
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define <vscale x 16 x i8> @sel_nxv16i8(<vscale x 16 x i1> %p,
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<vscale x 16 x i8> %dst,
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<vscale x 16 x i8> %a) {
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; CHECK-LABEL: sel_nxv16i8:
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; CHECK: mov z0.b, p0/m, z1.b
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; CHECK-NEXT: ret
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%sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %dst
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ret <vscale x 16 x i8> %sel
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}
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define <vscale x 8 x i16> @sel_nxv8i16(<vscale x 8 x i1> %p,
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<vscale x 8 x i16> %dst,
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<vscale x 8 x i16> %a) {
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; CHECK-LABEL: sel_nxv8i16:
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; CHECK: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %a, <vscale x 8 x i16> %dst
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ret <vscale x 8 x i16> %sel
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}
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define <vscale x 4 x i32> @sel_nxv4i32(<vscale x 4 x i1> %p,
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<vscale x 4 x i32> %dst,
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<vscale x 4 x i32> %a) {
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; CHECK-LABEL: sel_nxv4i32:
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; CHECK: mov z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %a, <vscale x 4 x i32> %dst
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ret <vscale x 4 x i32> %sel
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}
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define <vscale x 2 x i64> @sel_nxv2i64(<vscale x 2 x i1> %p,
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<vscale x 2 x i64> %dst,
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<vscale x 2 x i64> %a) {
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; CHECK-LABEL: sel_nxv2i64:
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; CHECK: mov z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %a, <vscale x 2 x i64> %dst
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ret <vscale x 2 x i64> %sel
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}
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; Floating point vector select
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define <vscale x 8 x half> @sel_nxv8f16(<vscale x 8 x i1> %p,
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<vscale x 8 x half> %dst,
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<vscale x 8 x half> %a) {
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; CHECK-LABEL: sel_nxv8f16:
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; CHECK: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %dst
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ret <vscale x 8 x half> %sel
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}
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define <vscale x 4 x float> @sel_nxv4f32(<vscale x 4 x i1> %p,
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<vscale x 4 x float> %dst,
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<vscale x 4 x float> %a) {
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; CHECK-LABEL: sel_nxv4f32:
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; CHECK: mov z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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%sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %dst
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ret <vscale x 4 x float> %sel
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}
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define <vscale x 2 x float> @sel_nxv2f32(<vscale x 2 x i1> %p,
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<vscale x 2 x float> %dst,
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<vscale x 2 x float> %a) {
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; CHECK-LABEL: sel_nxv2f32:
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; CHECK: mov z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> %a, <vscale x 2 x float> %dst
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ret <vscale x 2 x float> %sel
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}
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define <vscale x 2 x double> @sel_nxv8f64(<vscale x 2 x i1> %p,
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<vscale x 2 x double> %dst,
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<vscale x 2 x double> %a) {
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; CHECK-LABEL: sel_nxv8f64:
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; CHECK: mov z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %dst
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ret <vscale x 2 x double> %sel
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}
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