Daniel Sanders 97297770a6 [mips] Range check simm7. ... Summary: Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual encoding (it's a uimm7 except that 0x7f represents -1). Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18145 llvm-svn: 264056		2016-03-22 14:40:00 +00:00
..
AArch64	AArch64: remove CRC feature from Cyclone.	2016-02-24 18:10:17 +00:00
AMDGPU	[AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3	2016-03-18 15:35:51 +00:00
ARM	ARM: Support relative references using the PREL31 symbol variant.	2016-03-10 19:30:18 +00:00
AsmParser	[MCParser] Accept uppercase radix variants 0X and 0B	2016-03-18 18:22:07 +00:00
COFF	[codeview] Dump def range lengths in hex	2016-02-11 23:40:14 +00:00
Disassembler	[AMDGPU] add VI disassembler tests. NFC.	2016-03-17 17:56:33 +00:00
ELF	[ELF][gcc compatibility]: support section names with special characters (e.g. "/")	2016-03-22 11:23:15 +00:00
Hexagon	[Hexagon] Add handling fixups and instruction relaxation	2016-03-21 20:27:17 +00:00
MachO	[MachO] Extend the alt_entry support for aliases added in r263521 to	2016-03-15 04:20:49 +00:00
Markup	…
Mips	[mips] Range check simm7.	2016-03-22 14:40:00 +00:00
PowerPC	[Power9] Implement new vsx instructions: load, store instructions for vector and scalar	2016-03-08 03:49:13 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Sort relocs to avoid code corruption by linker optimization	2015-12-16 18:12:40 +00:00
X86	[llvm-objdump] Print <unknown> in place of instruction text if it couldn't be disassembled.	2016-03-18 16:26:48 +00:00