forked from OSchip/llvm-project
f2968d58cb
This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196 |
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| .. | ||
| insns-pcrel.txt | ||
| insns-z13-bad.txt | ||
| insns-z13.txt | ||
| insns-z14.txt | ||
| insns.txt | ||
| invalid-regs.txt | ||
| lit.local.cfg | ||
| trunc-01.txt | ||
| trunc-02.txt | ||
| trunc-03.txt | ||
| unmapped.txt | ||