llvm-project/llvm/test/MC/Disassembler/AMDGPU
Dmitry Preobrazhensky 0a1ff464e1 [AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier
See bug 36154: https://bugs.llvm.org/show_bug.cgi?id=36154

Differential Revision: https://reviews.llvm.org/D42847

Reviewers: cfang, artem.tamazov, arsenm
llvm-svn: 324237
2018-02-05 14:18:53 +00:00
..
aperture-regs.ll
buf_fmt_packed_d16.txt AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace. 2018-01-30 16:42:40 +00:00
buf_fmt_unpacked_d16.txt AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace. 2018-01-30 16:42:40 +00:00
dpp_vi.txt
ds_vi.txt [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32 2017-12-22 17:13:28 +00:00
exp_vi.txt [AMDGPU][MC] Fixed bugs in export instruction 2017-05-19 13:36:09 +00:00
flat_gfx9.txt [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiers 2017-12-29 13:55:11 +00:00
flat_vi.txt AMDGPU: Remove tfe bit from flat instruction definitions 2017-05-11 17:38:33 +00:00
gfx8_dasm_all.txt [AMDGPU][mc][tests] Updated generated lit tests for GFX8/9 2017-11-22 15:47:27 +00:00
gfx9_dasm_all.txt AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
lit.local.cfg
literal16_vi.txt [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler output 2017-05-10 13:00:28 +00:00
mac.txt AMDGPU: Fix crash when disassembling VOP3 mac 2017-04-10 17:58:06 +00:00
mimg_vi.txt [AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier 2018-02-05 14:18:53 +00:00
mov.txt
mtbuf_vi.txt [AMDGPU] Add intrinsics for tbuffer load and store 2017-06-22 16:29:22 +00:00
mubuf_vi.txt
nop.txt
sdwa_gfx9.txt [AMDGPU][MC][GFX9] Enable inline constants for SDWA operands 2018-01-17 14:00:48 +00:00
sdwa_vi.txt [AMDGPU] SDWA: remove omod src operand for VOP2b instructions 2017-11-21 14:11:59 +00:00
si-support.txt
smem_vi.txt
smrd_vi.txt
sop1_vi.txt [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support 2018-01-10 14:22:19 +00:00
sop2_vi.txt
sopc_vi.txt [AMDGPU][MC] Corrected disassembler to decode instructions with 2 literals 2017-05-19 14:27:52 +00:00
sopk_vi.txt
sopp_vi.txt
trap_gfx9.txt [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers 2017-12-22 15:18:06 +00:00
trap_vi.txt [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers 2017-12-22 15:18:06 +00:00
vintrp.txt
vop1.txt
vop1_gfx9.txt AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
vop1_vi.txt
vop2_vi.txt [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
vop3_gfx9.txt [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support 2018-01-10 14:22:19 +00:00
vop3_vi.txt [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes 2017-08-16 13:51:56 +00:00
vopc_vi.txt