llvm-project/llvm/test/CodeGen
Wang, Pengfei a3b52a9d13 [X86][AMX] Refactor for PostRA ldtilecfg pass.
This is a follow up of D99010. We didn't consider the live range of shape registers when hoist ldtilecfg. There maybe risks, e.g. we happen to insert it to an invalid range of some registers and get unexpected error.

This patch fixes this problem by storing the value to corresponding stack place of ldtilecfg after all its definition immediately.

This patch also fix a problem in previous code: If we don't have a ldtilecfg which dominates all AMX instructions, we cannot initialize shapes for other ldtilecfg.

There're still some optimization points left. E.g. eliminate unused mov instructions, break the def-use dependency before RA etc.

Reviewed By: LuoYuanke, xiangzhangllvm

Differential Revision: https://reviews.llvm.org/D99966
2021-04-14 10:08:23 +08:00
..
AArch64 [AArch64][GlobalISel] Mark G_CTPOP as legal for v16s8 and v8s8 2021-04-13 11:03:39 -07:00
AMDGPU [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
ARC
ARM StackProtector: ensure protection does not interfere with tail call frame. 2021-04-13 15:14:57 +01:00
AVR
BPF BPF: remove default .extern data section 2021-04-13 11:35:52 -07:00
Generic [Debug-Info] make fortran CHARACTER(1) type as valid unsigned type 2021-04-11 23:17:01 -04:00
Hexagon [Hexagon, test] Fix use of undef FileCheck var 2021-04-02 18:47:49 +01:00
Inputs
Lanai
M68k [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling 2021-03-19 16:02:31 +00:00
MIR [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
MSP430
Mips [MIPS, test] Fix use of undef FileCheck var 2021-04-02 00:59:49 +01:00
NVPTX [NVPTX] Handle bitcast and ASC(101) when trying to avoid argument copy. 2021-04-06 13:06:00 -07:00
PowerPC [PowerPC] Use correct node to get a super register from a subreg 2021-04-13 19:52:21 -05:00
RISCV [RISCV] Implement COPY for Zvlsseg registers 2021-04-13 18:55:51 -07:00
SPARC
SystemZ
Thumb Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
Thumb2 [ARM] Add a number of intrinsics for MVE lane interleaving 2021-04-12 17:23:02 +01:00
VE
WebAssembly [WebAssembly] Update v128.any_true 2021-04-11 11:13:16 -07:00
WinCFGuard
WinEH
X86 [X86][AMX] Refactor for PostRA ldtilecfg pass. 2021-04-14 10:08:23 +08:00
XCore [CodeGen] Report a normal instead of fatal error for label redefinition 2021-03-09 10:54:41 +00:00