maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/Mips/micromips
History
Stefan Maksimovic b3e7ed3b94 [mips] Define certain instructions in microMIPS32r3 
Instructions affected:
mthc1, mfhc1, add.d, sub.d, mul.d, div.d,
mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d

These instructions are now defined for
microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td
since they shared their encoding with those already defined
in microMIPS32r6InstrInfo.td and have been therefore
removed from the latter file.

Some instructions present in MicroMipsInstrFPU.td which
did not have both AFGR64 and FGR64 variants defined have
been altered to do so.

Differential revision: https://reviews.llvm.org/D42738

llvm-svn: 324584
 		2018-02-08 09:25:17 +00:00
..
invalid-wrong-error.s [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2 2017-12-20 11:02:42 +00:00
invalid.s [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
valid-fp64.s [mips] Define certain instructions in microMIPS32r3 2018-02-08 09:25:17 +00:00
valid.s [mips] Define certain instructions in microMIPS32r3 2018-02-08 09:25:17 +00:00