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AsmParser
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[RISCV] Change parseVTypeI function
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2021-02-12 19:38:34 +08:00 |
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Disassembler
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[RISCV] Fix shared libs build
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2021-02-09 06:14:25 -06:00 |
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MCTargetDesc
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[MC][RISCV] Support .reloc *, BFD_RELOC_{NONE,32,64}, *
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2021-03-05 21:45:11 -08:00 |
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TargetInfo
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llvmbuildectomy - replace llvm-build by plain cmake
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2020-11-13 10:35:24 +01:00 |
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CMakeLists.txt
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[RISCV] Merge Utils library into MCTargetDesc
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2021-01-14 11:47:30 -08:00 |
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RISCV.h
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[RISCV] Merge Utils library into MCTargetDesc
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2021-01-14 11:47:30 -08:00 |
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RISCV.td
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[RISCV] Fix name of Zba extension (NFC)
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2021-01-24 21:02:34 +00:00 |
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RISCVAsmPrinter.cpp
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[RISCV] Add -mtune support
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2020-10-16 13:55:08 +08:00 |
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RISCVCallLowering.cpp
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[GlobalISel] Base implementation for sret demotion.
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2021-01-06 10:30:50 +05:30 |
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RISCVCallLowering.h
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[GlobalISel] Base implementation for sret demotion.
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2021-01-06 10:30:50 +05:30 |
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RISCVCallingConv.td
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…
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RISCVCleanupVSETVLI.cpp
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[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli
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2021-02-25 07:51:19 -08:00 |
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RISCVExpandAtomicPseudoInsts.cpp
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[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
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2020-07-15 10:50:55 +01:00 |
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RISCVExpandPseudoInsts.cpp
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[RISCV] Add new vector instructions in v0.10.
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2021-02-03 13:28:58 +08:00 |
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RISCVFrameLowering.cpp
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[RISCV] Simplify BP initialisation
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2021-02-17 20:33:20 +08:00 |
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RISCVFrameLowering.h
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[RISCV] Frame handling for RISC-V V extension.
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2021-02-17 14:05:19 +08:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Fix crash when inserting large fixed-length subvectors
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2021-03-04 09:27:16 +00:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Use a ComplexPattern for zexti32 to match sexti32.
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2021-02-24 16:06:29 -08:00 |
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RISCVISelLowering.cpp
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[RISCV] Make use of DAG.getNeutralElement in lowerVECREDUCE to avoid repeating the same list of constants. NFC
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2021-03-08 09:11:10 -08:00 |
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RISCVISelLowering.h
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[RISCV] Add new entry points to getContainerForFixedLengthVector
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2021-03-08 09:26:19 +00:00 |
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RISCVInstrFormats.td
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[RISCV] Make scalable vector FMA commutable for register allocation.
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2021-02-08 10:05:33 -08:00 |
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RISCVInstrFormatsC.td
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…
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RISCVInstrFormatsV.td
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[RISCV] Add new vector instructions in v0.10.
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2021-02-03 13:28:58 +08:00 |
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RISCVInstrInfo.cpp
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[RISCV] Spilling for RISC-V V extension. (2nd version)
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2021-02-17 14:05:19 +08:00 |
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RISCVInstrInfo.h
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[RISCV] Frame handling for RISC-V V extension.
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2021-02-17 14:05:19 +08:00 |
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RISCVInstrInfo.td
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[RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode.
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2021-03-08 09:06:56 -08:00 |
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RISCVInstrInfoA.td
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[RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode.
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2021-03-08 09:06:56 -08:00 |
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RISCVInstrInfoB.td
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[RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64
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2021-02-19 10:07:12 -08:00 |
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RISCVInstrInfoC.td
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[RISCV] More whitespace and comment typo fixes in RISCVInstrInfoC.td
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2021-02-11 02:32:36 +00:00 |
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RISCVInstrInfoD.td
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[RISCV] Use a ComplexPattern for zexti32 to match sexti32.
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2021-02-24 16:06:29 -08:00 |
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RISCVInstrInfoF.td
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[RISCV] Use a ComplexPattern for zexti32 to match sexti32.
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2021-02-24 16:06:29 -08:00 |
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RISCVInstrInfoM.td
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[RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode.
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2021-03-08 09:06:56 -08:00 |
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RISCVInstrInfoV.td
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[RISCV] vle1.v/vse1.v should be unmasked instructions.
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2021-02-23 19:59:22 +08:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV] Update RVV ISA section-header comments. NFC.
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2021-02-25 14:15:28 +00:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Preserve fixed-length VL on insert_vector_elt in more cases
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2021-03-04 09:21:10 +00:00 |
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RISCVInstrInfoVVLPatterns.td
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[RISCV] Preserve fixed-length VL on insert_vector_elt in more cases
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2021-03-04 09:21:10 +00:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Use a ComplexPattern for zexti32 to match sexti32.
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2021-02-24 16:06:29 -08:00 |
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RISCVInstructionSelector.cpp
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RISCV: Avoid GlobalISel build break in a future patch
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2020-07-13 14:01:57 -04:00 |
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RISCVLegalizerInfo.cpp
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…
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RISCVLegalizerInfo.h
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…
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RISCVMCInstLower.cpp
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[RISCV] Define different pseudo instructions for different FPR.
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2021-01-26 15:48:35 +08:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Frame handling for RISC-V V extension.
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2021-02-17 14:05:19 +08:00 |
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RISCVMergeBaseOffset.cpp
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[RISCV] Support Zfh half-precision floating-point extension.
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2020-12-03 09:16:33 +08:00 |
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RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Improve register allocation around vector masks
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2021-02-20 14:47:51 +00:00 |
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RISCVRegisterInfo.h
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[RISCV] Improve register allocation around vector masks
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2021-02-20 14:47:51 +00:00 |
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RISCVRegisterInfo.td
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[RISCV] Use XLenRI alias for RegInfoByHwMode instances
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2021-02-18 19:38:36 +00:00 |
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RISCVSchedRocket.td
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[RISCV] Fix formatting (NFC)
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2020-09-25 18:15:04 -05:00 |
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RISCVSchedSiFive7.td
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[RISCV] Use the commercial name for scheduling model (NFC)
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2020-10-23 16:33:27 -05:00 |
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RISCVSchedule.td
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[RISCV] Fix formatting (NFC)
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2020-09-25 18:15:04 -05:00 |
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RISCVSubtarget.cpp
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[RISCV] Add support loads, stores, and splats of vXi1 fixed vectors.
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2021-02-11 09:13:16 -08:00 |
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RISCVSubtarget.h
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[RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other.
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2021-02-09 10:47:23 -08:00 |
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RISCVSystemOperands.td
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[RISCV] Enable the use of the old mucounteren name
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2020-08-17 13:11:49 +01:00 |
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RISCVTargetMachine.cpp
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[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.
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2021-03-02 12:55:51 -08:00 |
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RISCVTargetMachine.h
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[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
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2020-12-18 21:50:55 +00:00 |
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RISCVTargetObjectFile.cpp
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ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects
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2021-02-26 16:38:44 -08:00 |
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other.
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2021-02-09 10:47:23 -08:00 |
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RISCVTargetTransformInfo.h
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[RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector
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2021-03-05 10:54:51 +08:00 |
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