llvm-project/llvm/test/CodeGen/AMDGPU
Matt Arsenault 0e0a1c80fb AMDGPU: Correct behavior of f16/i16 non-format store intrinsics
This was switching to use a format store for a non-format store for
f16 types. Also fixes i16/f16 stores on targets without legal f16.

The corresponding loads also need to be fixed.

llvm-svn: 367872
2019-08-05 14:57:59 +00:00
..
GlobalISel AMDGPU/GlobalISel: Alternative mappings for constants 2019-08-05 14:40:26 +00:00
32-bit-local-address-space.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
InlineAsmCrash.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
README
accvgpr-copy.mir [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
add-debug.ll
add.i16.ll
add.ll AMDGPU: Select VOP3 form of add 2019-05-08 22:09:57 +00:00
add.v2i16.ll AMDGPU: Undo sub x, c canonicalization for v2i16 2019-06-19 23:37:43 +00:00
add3.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
add_i1.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
add_i64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
add_i128.ll
add_shl.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
addrspacecast-captured.ll AMDGPU: Fix using old address spaces in some tests 2018-12-05 17:34:59 +00:00
addrspacecast-constantexpr.ll [FunctionAttrs] Annotate "willreturn" for intrinsics 2019-07-28 06:09:56 +00:00
addrspacecast.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
adjust-writemask-invalid-copy.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
agpr-register-count.ll [AMDGPU] use v32f32 for 3 mfma intrinsics 2019-07-12 22:42:01 +00:00
alignbit-pat.ll
alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
always-uniform.ll
amdgcn-ieee.ll AMDGPU: Remove dx10-clamp from subtarget features 2019-03-29 19:14:54 +00:00
amdgcn.bitcast.ll AMDGPU: Make v4i16/v4f16 legal 2018-06-15 15:15:46 +00:00
amdgcn.private-memory.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
amdgpu-alias-analysis.ll AMDGPU: Improve alias analysis for GDS 2019-07-17 11:22:19 +00:00
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-i16-to-i32.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
amdgpu-codegenprepare-idiv.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
amdgpu-codegenprepare-mul24.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
amdgpu-function-calls-option.ll AMDGPU: Enable function calls by default 2019-02-28 00:40:32 +00:00
amdgpu-inline.ll [AMDGPU] Tune inlining parameters for AMDGPU target 2019-07-17 16:51:29 +00:00
amdgpu-shader-calling-convention.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
amdgpu.private-memory.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
amdgpu.work-item-intrinsics.deprecated.ll
amdhsa-trap-num-sgprs.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
amdpal-cs.ll
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-msgpack-cs.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-es.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-gs.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-hs.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-ls.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-ps.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-psenable.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-msgpack-vs.ll [AMDGPU] Added MsgPack format PAL metadata 2019-03-20 18:47:21 +00:00
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll [AMDGPU] Fix CS scratch setup on pre-GCN3 ASICs 2019-02-08 15:41:11 +00:00
amdpal_scratch_mergedshader.ll [AMDGPU] Enable LICM in the BE pipeline 2018-06-29 16:26:53 +00:00
and-gcn.ll
and.ll [DAGCombine] Prune unnused nodes. 2019-03-29 17:35:56 +00:00
and_or.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
andorbitset.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
andorn2.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
andorxorinvimm.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
annotate-kernel-features-hsa-call.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
annotate-kernel-features-hsa.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
annotate-kernel-features.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
are-loads-from-same-base-ptr.ll AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics 2019-03-27 15:41:00 +00:00
array-ptr-calc-i32.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
array-ptr-calc-i64.ll AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt 2017-11-13 22:55:05 +00:00
ashr.v2i16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
atomic_cmp_swap_local.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
atomic_load_add.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_load_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
atomic_load_sub.ll [AMDGPU] Add an AMDGPU specific atomic optimizer. 2018-10-08 15:49:19 +00:00
atomic_optimizations_buffer.ll [AMDGPU] Simplify the exclusive scan used for optimized atomics 2019-07-19 08:40:37 +00:00
atomic_optimizations_global_pointer.ll [AMDGPU] Fix DPP combiner check for exec modification 2019-07-12 15:59:40 +00:00
atomic_optimizations_local_pointer.ll [AMDGPU] Optimize atomic AND/OR/XOR 2019-07-17 13:40:03 +00:00
atomic_optimizations_pixelshader.ll [AMDGPU] Fix DPP combiner check for exec modification 2019-07-12 15:59:40 +00:00
atomic_optimizations_raw_buffer.ll [AMDGPU] Fix DPP combiner check for exec modification 2019-07-12 15:59:40 +00:00
atomic_optimizations_struct_buffer.ll [AMDGPU] Fix DPP combiner check for exec modification 2019-07-12 15:59:40 +00:00
atomic_store_local.ll AMDGPU: Add patterns for i32/i64 local atomic load/store 2018-06-22 08:39:52 +00:00
atomicrmw-nand.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
attr-amdgpu-flat-work-group-size-v3.ll [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
attr-amdgpu-flat-work-group-size.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
attr-amdgpu-num-sgpr-spill-to-smem.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
attr-amdgpu-num-sgpr.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll [AMDGPU] more gfx1010 tests. NFC. 2019-06-12 18:44:11 +00:00
basic-call-return.ll AMDGPU: Fix register name format in tests 2018-03-27 18:39:42 +00:00
basic-loop.ll
bfe-combine.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
bfe-patterns.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
bfe_uint.ll
bfi_int.ll AMDGPU: Scalarize vector argument types to calls 2018-07-31 19:05:14 +00:00
bfm.ll
big_alu.ll
bitcast-constant-to-vector.ll AMDGPU: Fix assertion with bitcast from i64 constant to v4i16 2018-11-02 02:43:55 +00:00
bitcast-v4f16-v4i16.ll AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts 2018-12-19 22:53:33 +00:00
bitcast-vector-extract.ll IR: Add immarg attribute 2019-03-12 21:02:54 +00:00
bitreverse-inline-immediates.ll
bitreverse.ll [DAG] Add SimplifyDemandedBits support for BITREVERSE 2019-05-11 20:56:05 +00:00
br_cc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
branch-relaxation-debug-info.ll AMDGPU: Skip debug instructions in assert 2019-04-22 19:14:26 +00:00
branch-relaxation-inst-size-gfx10.ll MC: Allow getMaxInstLength to depend on the subtarget 2019-05-22 16:28:41 +00:00
branch-relaxation.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
branch-uniformity.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
break-smem-soft-clauses.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
break-vmem-soft-clauses.mir AMDGPU: Assume xnack is enabled by default 2019-05-16 14:48:34 +00:00
bswap.ll AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
buffer-schedule.ll [AMDGPU] stop buffer_store being moved illegally 2018-02-20 10:03:38 +00:00
bug-vopc-commute.ll AMDGPU: Convert tests away from llvm.SI.load.const 2019-01-17 22:47:26 +00:00
build-vector-insert-elt-infloop.ll AMDGPU: Move d16 load matching to preprocess step 2019-03-08 20:58:11 +00:00
build-vector-packed-partial-undef.ll AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
build_vector.ll
byval-frame-setup.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
call-argument-types.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
call-constexpr.ll [AMDGPU] Packed thread ids in function call ABI 2019-06-28 01:52:13 +00:00
call-encoding.ll
call-graph-register-usage.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
call-preserved-registers.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
call-return-types.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
call-skip.ll AMDGPU: Force skip branches over calls 2019-05-20 22:04:42 +00:00
call-to-kernel-undefined.ll AMDGPU: Fix crashes in invalid call cases 2019-02-28 00:28:44 +00:00
call-to-kernel.ll AMDGPU: Fix crashes in invalid call cases 2019-02-28 00:28:44 +00:00
call-waitcnt.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
call_fs.ll
callee-frame-setup.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
callee-special-input-sgprs.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
callee-special-input-vgprs.ll [AMDGPU] Test update. NFC. 2019-07-22 18:08:53 +00:00
calling-conventions.ll AMDGPU: Don't assert on v4f16 arguments to shader calling conventions 2019-07-25 13:55:07 +00:00
captured-frame-index.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
cayman-loop-bug.ll
cf-loop-on-constant.ll AMDGPU: Try a lot harder to emit scalar loads 2018-06-07 09:54:49 +00:00
cf-stack-bug.ll
cf_end.ll
cgp-addressing-modes-flat.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
cgp-addressing-modes.ll CodeGenPrep: preserve inbounds attribute when sinking GEPs. 2019-03-12 15:22:23 +00:00
cgp-bitfield-extract.ll [DAGCombiner] re-enable truncation of binops 2018-12-08 16:07:38 +00:00
chain-hi-to-lo.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
clamp-modifier.ll AMDGPU: Improve hack for packing conversion ops 2018-08-01 20:13:58 +00:00
clamp-omod-special-case.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
clamp.ll AMDGPU: Remove dx10-clamp from subtarget features 2019-03-29 19:14:54 +00:00
cluster-flat-loads-postra.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
cluster-flat-loads.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
cndmask-no-def-vcc.ll [DAG] add undef simplifications for select nodes 2018-11-18 17:36:23 +00:00
coalescer-extend-pruned-subrange.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
coalescer-identical-values-undef.mir Improve handling of COPY instructions with identical value numbers 2018-06-25 13:46:41 +00:00
coalescer-subranges-another-copymi-not-live.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
coalescer-subranges-another-prune-error.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
coalescer-subranges-prune-kill-copy.mir Fix register coalescer failure to prune value 2019-05-21 19:32:41 +00:00
coalescer-subreg-join.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
coalescer-subregjoin-fullcopy.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
coalescer-with-subregs-bad-identical.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
coalescer_distribute.ll AMDGPU: Don't use spir_kernel in a test 2018-07-05 17:01:29 +00:00
coalescer_remat.ll
coalescing-with-subregs-in-loop-bug.mir AMDGPU: Fix missing scc implicit def on s_andn2_b64_term 2019-03-27 16:58:22 +00:00
code-object-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
codegen-prepare-addrmode-sext.ll
collapse-endcf-broken.mir AMDGPU: Add additional MIR tests for exec mask optimizations 2019-03-27 16:58:30 +00:00
collapse-endcf.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
collapse-endcf.mir Reapply "AMDGPU: Split block for si_end_cf" 2019-08-01 01:25:27 +00:00
collapse-endcf2.mir AMDGPU: Assume calls read exec 2019-05-21 23:23:16 +00:00
combine-and-sext-bool.ll
combine-cond-add-sub.ll [AMDGPU] fix commuted case of sub combine 2019-02-21 02:58:00 +00:00
combine-ftrunc.ll
combine_vloads.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
comdat.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
commute-compares.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
commute-shifts.ll [Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold 2019-07-24 22:57:22 +00:00
commute_modifiers.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
complex-folding.ll
computeKnownBits-scalar-to-vector-crash.ll [SelectionDAG] Don't pass on DemandedElts when handling SCALAR_TO_VECTOR 2018-12-07 09:18:44 +00:00
concat_vectors.ll DAG: Fix creating concat_vectors with illegal type 2018-06-15 12:09:15 +00:00
constant-address-space-32bit.ll AMDGPU: Fix folding immediate into readfirstlane through reg_sequence 2019-06-19 20:44:15 +00:00
constant-fold-imm-immreg.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
constant-fold-mi-operands.ll AMDGPU: Explicitly define a triple for some tests 2019-06-17 19:25:57 +00:00
control-flow-fastregalloc.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
control-flow-optnone.ll Revert "StructurizeCFG: Test for branch divergence correctly" 2018-02-24 17:29:09 +00:00
convergent-inlineasm.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
copy-illegal-type.ll [DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target. 2018-08-28 03:47:20 +00:00
copy-to-reg.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
couldnt-join-subrange-3.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
cross-block-use-is-not-abi-copy.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
csr-gfx10.ll AMDGPU: Fix not marking new gfx10 SGPRs as CSRs 2019-05-21 23:23:05 +00:00
ctlz.ll [AMDGPU] Regenerate CTLZ tests for an upcoming patch 2019-05-31 15:06:14 +00:00
ctlz_zero_undef.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ctpop64.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
cttz_zero_undef.ll [DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into cttz_zero_undef/ctlz_zero_undef if we can prove the input is never zero 2018-02-06 23:54:37 +00:00
cube.ll
cvt_f32_ubyte.ll AMDGPU: Select VOP3 form of add 2019-05-08 22:09:57 +00:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dag-divergence.ll AMDGPU: Fix DAG divergence not reporting flat loads 2018-09-04 18:58:19 +00:00
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll [AMDGPU] Early expansion of 32 bit udiv/urem 2018-06-28 15:59:18 +00:00
dagcombine-setcc-select.ll [AMDGPU] Disable DAG combine at -O0 2018-11-27 15:13:37 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dce-disjoint-intervals.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
dead-lane.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
dead-mi-use-same-intr.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
dead_copy.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
debug-value-scheduler-crash.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
debug-value.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
debug-value2.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
debug.ll [AMDGPU] Fix +DumpCode to print an entry label for the first function 2019-06-27 08:19:28 +00:00
default-fp-mode.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
detect-dead-lanes.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
directive-amdgcn-target.ll AMDGPU: Make sram-ecc off by default for Vega20 2019-03-29 12:04:18 +00:00
disable_form_clauses.ll [AMDGPU] Added target-specific attribute amdgpu-max-memory-clause 2019-05-30 18:46:34 +00:00
disconnected-predset-break-bug.ll
div_i128.ll [Testing] Fix tests that break with read-only checkouts 2019-08-01 06:41:40 +00:00
diverge-extra-formal-args.ll [AMDGPU] Fix issues for backend divergence tracking 2018-04-18 13:53:31 +00:00
diverge-interp-mov-lower.ll [AMDGPU] Fix issues for backend divergence tracking 2018-04-18 13:53:31 +00:00
diverge-switch-default.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
divergence-at-use.ll [AMDGPU] Add amdgpu_kernel for consistency with other tests 2019-07-29 11:48:17 +00:00
divergent-branch-uniform-condition.ll [AMDGPU] LCSSA pass added in preISel. Uniform values defined in the divergent loop and used outside 2019-07-02 17:59:44 +00:00
divrem24-assume.ll [AMDGPU] Use AssumptionCacheTracker in the divrem32 expansion 2018-07-25 17:02:11 +00:00
dpp_combine.mir [AMDGPU] Fix DPP combiner check for exec modification 2019-07-12 15:59:40 +00:00
drop-mem-operand-move-smrd.ll
ds-combine-large-stride.ll [AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32_e64 2018-01-22 21:46:43 +00:00
ds-combine-with-dependence.ll AMDGPU: Correct DS implementation of areLoadsFromSameBasePtr 2019-03-08 20:30:50 +00:00
ds-negative-offset-addressing-mode-loop.ll AMDGPU: Select VOP3 form of add 2019-05-08 22:09:57 +00:00
ds-sub-offset.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
ds_read2.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
ds_read2_offset_order.ll
ds_read2_superreg.ll
ds_read2st64.ll AMDGPU: Use gfx9 carry-less add/sub instructions 2017-11-30 22:51:26 +00:00
ds_write2.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
ds_write2st64.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
dynamic_stackalloc.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
early-if-convert-cost.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
early-if-convert.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
early-inline-alias.ll
early-inline.ll Reapply "AMDGPU: Force inlining if LDS global address is used" 2018-07-10 14:03:41 +00:00
elf-header-flags-mach.ll [AMDGPU] gfx908 target 2019-07-09 18:10:06 +00:00
elf-header-flags-sram-ecc.ll [AMDGPU] gfx908 target 2019-07-09 18:10:06 +00:00
elf-header-flags-xnack.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf-header-osabi.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf-notes.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf.metadata.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf.r600.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
else.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
empty-function.ll
enable-no-signed-zeros-fp-math.ll Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control 2019-07-31 21:57:28 +00:00
endcf-loop-header.ll
endpgm-dce.mir AMDGPU: Add some tests for inlineasm behavior 2019-05-21 23:23:12 +00:00
enqueue-kernel.ll [AMDGPU] Change enqueue kernel handle type 2018-06-13 17:31:51 +00:00
exceed-max-sgprs.ll
extend-bit-ops-i16.ll
extload-align.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extload-private.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
extload.ll
extract-lowbits.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
extract-subvector-equal-length.ll [CodeGen] Fix assert in SelectionDAG::computeKnownBits 2018-08-13 18:44:21 +00:00
extract-vector-elt-build-vector-combine.ll
extract_subvector_vec4_vec3.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
extract_vector_dynelt.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
extract_vector_elt-f16.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extract_vector_elt-f64.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
extract_vector_elt-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
extract_vector_elt-i16.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
extract_vector_elt-i64.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
extractelt-to-trunc.ll [AMDGPU] Regenerate extractelt->truncate test. 2019-04-19 09:49:04 +00:00
fabs.f16.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fabs.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
fadd-fma-fmul-combine.ll
fadd.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fadd.ll Utilize new SDNode flag functionality to expand current support for fadd 2018-06-18 23:44:59 +00:00
fadd64.ll
fcanonicalize-elimination.ll [AMDGPU] Fix for vector element insertion 2019-02-01 16:51:09 +00:00
fcanonicalize.f16.ll DAG: Handle odd vector sizes in calling conv splitting 2018-09-10 11:49:23 +00:00
fcanonicalize.ll [AMDGPU] gfx1010 tests. NFC. 2019-05-13 19:30:06 +00:00
fceil.ll
fceil64.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fcmp.ll
fcmp64.ll
fconst64.ll
fcopysign.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f32.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fcopysign.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fdiv.f16.ll [AMDGPU] gfx1010: use fmac instructions 2019-05-04 04:20:37 +00:00
fdiv.f64.ll
fdiv.ll
fdiv32-to-rcp-folding.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
fdot2.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
fence-barrier.ll AMDGPU: Select VOP3 form of add 2019-05-08 22:09:57 +00:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
fexp.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
ffloor.f64.ll Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control 2019-07-31 21:57:28 +00:00
ffloor.ll
fix-sgpr-copies.mir [AMDGPU] Fix the mis-handling of `vreg_1` copied from scalar register. 2019-05-28 16:29:39 +00:00
fix-vgpr-copies.mir Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
fix-wwm-vgpr-copy.ll [AMDGPU] Fix a weird WWM intrinsic issue. 2019-01-29 14:28:17 +00:00
flat-address-space.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
flat-error-unsupported-gpu-hsa.ll Fix flat-error-unsupported-gpu-hsa test 2019-03-18 19:38:04 +00:00
flat-for-global-subtarget-feature.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
flat-load-clustering.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
flat-offset-bug.ll [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
flat-scratch-reg.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
flat_atomics.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
flat_atomics_i64.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
floor.ll
fma-combine.ll AMDGPU: Fix -enable-var-scope violations 2017-11-12 23:53:44 +00:00
fma.f64.ll
fma.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmac.sdwa.ll [AMDGPU] Enable v4f16 and above for v_pk_fma instructions 2019-07-29 08:15:10 +00:00
fmad.ll
fmax.ll
fmax3.f64.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax3.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmax_legacy.f16.ll [DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support 2019-07-11 14:45:03 +00:00
fmax_legacy.f64.ll AMDGPU: Cleanup min/max legacy tests 2018-08-12 19:29:53 +00:00
fmax_legacy.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmaxnum.f64.ll
fmaxnum.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmaxnum.r600.ll AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests 2018-07-31 20:38:42 +00:00
fmed3.ll AMDGPU: Don't form fmed3 if it will require materialization 2018-09-18 02:34:54 +00:00
fmin.ll
fmin3.ll [AMDGPU] Ban i8 min3 promotion. 2019-03-19 15:50:24 +00:00
fmin_fmax_legacy.amdgcn.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fmin_legacy.f16.ll [DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support 2019-07-11 14:45:03 +00:00
fmin_legacy.f64.ll AMDGPU: Cleanup min/max legacy tests 2018-08-12 19:29:53 +00:00
fmin_legacy.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
fminnum.f64.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
fminnum.r600.ll AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests 2018-07-31 20:38:42 +00:00
fmul-2-combine-multi-use.ll [AMDGPU] more gfx1010 tests. NFC. 2019-06-12 18:44:11 +00:00
fmul.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fmul.ll
fmul64.ll
fmuladd.f16.ll [AMDGPU] gfx1010: use fmac instructions 2019-05-04 04:20:37 +00:00
fmuladd.f32.ll AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
fmuladd.f64.ll
fmuladd.v2f16.ll [AMDGPU] Enabled v2.16 literals for VOP3P 2018-04-17 23:09:05 +00:00
fnearbyint.ll
fneg-combines.ll Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control 2019-07-31 21:57:28 +00:00
fneg-combines.si.ll AMDGPU: Address todo for handling 1/(2 pi) 2018-08-15 21:03:55 +00:00
fneg-fabs.f16.ll [DAGCombine] GetNegatedExpression - constant float vector support (PR42105) 2019-06-11 09:44:33 +00:00
fneg-fabs.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg-fabs.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
fneg.f16.ll AMDGPU: Use scalar operations for f16 fabs/fneg patterns 2018-06-07 10:15:20 +00:00
fneg.f64.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fneg.ll
fold-cndmask.mir [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers 2019-03-18 19:25:39 +00:00
fold-fi-mubuf.mir AMDGPU: Fold frame index into MUBUF 2019-06-24 14:53:56 +00:00
fold-fi-operand-shrink.mir AMDGPU: Support shrinking add with FI in SIFoldOperands 2019-05-03 15:21:53 +00:00
fold-fmul-to-neg-abs.ll
fold-imm-copy.mir AMDGPU: Fix test verification 2019-05-03 13:42:55 +00:00
fold-imm-f16-f32.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
fold-immediate-operand-shrink-with-carry.mir [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic 2019-03-18 19:35:44 +00:00
fold-immediate-operand-shrink.mir AMDGPU: Replace shrunk instruction with dummy implicit_def 2019-05-03 14:40:10 +00:00
fold-immediate-output-mods.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
fold-implicit-operand.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
fold-multiple.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
fold-operands-order.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fold-readlane.mir AMDGPU: Fix folding immediate into readfirstlane through reg_sequence 2019-06-19 20:44:15 +00:00
fold-vgpr-copy.mir [AMDGPU] Fold copy (copy vgpr) 2018-09-27 18:55:20 +00:00
force-alwaysinline-lds-global-address-codegen.ll AMDGPU: Always run AMDGPUAlwaysInline 2018-10-03 02:47:25 +00:00
force-alwaysinline-lds-global-address.ll AMDGPU: Enable function calls by default 2019-02-28 00:40:32 +00:00
fp-atomic-to-s_denormmode.mir [AMDGPU] hazard recognizer for fp atomic to s_denorm_mode 2019-06-21 16:30:14 +00:00
fp-classify.ll AMDGPU: Combine and of seto/setuo and fp_class 2018-08-10 18:58:56 +00:00
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fp_to_uint.f64.ll
fp_to_uint.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fpext-free.ll AMDGPU: Fix V_FMA_F16 selection on GFX9 2018-11-19 21:10:16 +00:00
fpext.f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
fpext.ll
fptosi.f16.ll
fptoui.f16.ll
fptrunc.f16.ll AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-elimination.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
frame-lowering-entry-all-sgpr-used.mir [AMDGPU] Skip calculating callee saved registers for entry function. 2019-07-11 23:53:30 +00:00
frame-lowering-fp-adjusted.mir [AMDGPU] Add the adjusted FP as a livein register. 2019-07-16 15:57:12 +00:00
frem.ll
fsqrt.f64.ll
fsqrt.ll
fsub.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
fsub.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
fsub64.ll
ftrunc.f64.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
ftrunc.ll
function-args.ll AMDGPU: Don't fix emergency stack slot at offset 0 2019-06-05 22:37:50 +00:00
function-call-relocs.ll [AMDGPU] Support emitting GOT relocations for function calls 2019-02-04 20:00:07 +00:00
function-returns.ll AMDGPU: Add some function return test cases 2019-07-19 16:45:48 +00:00
gds-atomic.ll AMDGPU: Support GDS atomics 2019-07-01 17:17:45 +00:00
gep-address-space.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
gfx10-vop-literal.ll [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
gfx902-without-xnack.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
global-constant.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
global-directive.ll
global-extload-i16.ll
global-load-store-atomics.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
global-saddr.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
global-smrd-unknown.ll AMDGPU: Don't use undef in a test 2018-05-08 18:43:34 +00:00
global-variable-relocs.ll
global_atomics.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
global_atomics_i64.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
global_smrd.ll AMDGPU: Use GOT PSV since it has an address space now 2018-09-10 02:23:39 +00:00
global_smrd_cfg.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
gv-const-addrspace.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
gv-offset-folding.ll
gws-hazards.mir Reapply "AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics" 2019-06-19 19:55:27 +00:00
half.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
hazard-buffer-store-v-interp.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
hazard-hidden-bundle.mir [AMDGPU] Enable serializing of argument info. 2019-07-03 02:00:21 +00:00
hazard-in-bundle.mir [AMDGPU] gfx1010: small test change for wave32. NFC 2019-06-13 19:05:04 +00:00
hazard-inlineasm.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
hazard-kill.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
hazard.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
hoist-cond.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
hsa-default-device.ll
hsa-fp-mode.ll AMDGPU: Remove dx10-clamp from subtarget features 2019-03-29 19:14:54 +00:00
hsa-func-align.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-func.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-globals.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-deduce-ro-arg.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-enqueue-kernel-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-enqueue-kernel.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-from-llvm-ir-full-v3.ll [AMDGPU] Added a new metadata for multi grid sync implicit argument 2019-07-05 16:05:17 +00:00
hsa-metadata-from-llvm-ir-full.ll [AMDGPU] Added a new metadata for multi grid sync implicit argument 2019-07-05 16:05:17 +00:00
hsa-metadata-hidden-args-v3.ll [AMDGPU] Added a new metadata for multi grid sync implicit argument 2019-07-05 16:05:17 +00:00
hsa-metadata-hidden-args.ll [AMDGPU] Added a new metadata for multi grid sync implicit argument 2019-07-05 16:05:17 +00:00
hsa-metadata-images-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-images.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-1-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-1.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-2-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-2.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-3-v3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-3.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-kernel-code-props-v3.ll [AMDGPU] Fix high occupancy calculation and print it 2019-07-31 01:07:10 +00:00
hsa-metadata-kernel-code-props.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
hsa-metadata-wavefrontsize.ll [AMDGPU] gfx1010 wave32 metadata 2019-06-17 16:48:56 +00:00
hsa-note-no-func.ll [AMDGPU] gfx908 target 2019-07-09 18:10:06 +00:00
hsa.ll [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
huge-private-buffer.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
i1-copies-rpo.mir AMDGPU: Make fixing i1 copies robust against re-ordering 2019-06-27 16:56:44 +00:00
i1-copy-from-loop.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
i1-copy-implicit-def.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
i1-copy-phi-uniform-branch.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
i1-copy-phi.ll [SelectionDAG] Enhance the simplification of `copyto` from `implicit-def`. 2019-05-27 18:26:29 +00:00
i8-to-double-to-float.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
icmp64.ll
idiv-licm.ll [AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32 2019-05-06 22:27:05 +00:00
idot2.ll [AMDGPU] Regenerate idot tests. NFCI. 2019-07-11 10:37:58 +00:00
idot4s.ll [TargetLowering] Add SimplifyMultipleUseDemandedBits 2019-07-23 12:39:08 +00:00
idot4u.ll [TargetLowering] Add SimplifyMultipleUseDemandedBits 2019-07-23 12:39:08 +00:00
idot8s.ll [SelectionDAG] Check for any recursion depth greater than or equal to limit instead of just equal the limit. 2019-07-27 12:48:46 +00:00
idot8u.ll [SelectionDAG] Check for any recursion depth greater than or equal to limit instead of just equal the limit. 2019-07-27 12:48:46 +00:00
illegal-sgpr-to-vgpr-copy.ll [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
image-attributes.ll
image-resource-id.ll
image-schedule.ll AMDGPU: Fix some outdated datalayouts in tests 2018-09-13 11:56:28 +00:00
image_ls_mipmap_zero.ll [AMDGPU] Optimize image_[load|store]_mip 2019-06-10 15:58:51 +00:00
img-nouse-adjust.ll [AMDGPU] Allow MIMG with no uses in adjustWritemask in isel 2019-03-20 09:29:55 +00:00
imm.ll [AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operands 2019-01-18 15:17:17 +00:00
imm16.ll [DAGCombiner] allow narrowing of add followed by truncate 2018-12-22 17:10:31 +00:00
immv216.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
implicit-def-muse.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
indirect-addressing-si-gfx9.ll [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instructions s_set_gpr_idx_on and s_set_gpr_idx_mode 2019-02-27 13:12:12 +00:00
indirect-addressing-si-noopt.ll [AMDGPU] Disable DAG combine at -O0 2018-11-27 15:13:37 +00:00
indirect-addressing-si-pregfx9.ll [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instructions s_set_gpr_idx_on and s_set_gpr_idx_mode 2019-02-27 13:12:12 +00:00
indirect-addressing-si.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
indirect-addressing-term.ll RegAllocFast: Improve hinting heuristic 2019-05-16 12:50:39 +00:00
indirect-private-64.ll AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements 2018-02-16 19:14:17 +00:00
infer-addrpace-pipeline.ll
infinite-loop-evergreen.ll
infinite-loop.ll [MachineLICM][X86][AMDGPU] Fix subtle bug in the updating of PhysRegClobbers in post-RA LICM 2018-12-05 03:41:26 +00:00
inline-asm.ll [AMDGPU] Correct the handling of inlineasm output registers. 2019-05-28 19:37:09 +00:00
inline-attr.ll Add, and infer, a nofree function attribute 2019-07-08 15:57:56 +00:00
inline-calls.ll AMDGPU: Enable function calls by default 2019-02-28 00:40:32 +00:00
inline-constraints.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
inline-maxbb.ll [AMDGPU] Don't constrain callees with inlinehint from inlining on MaxBB check 2019-06-14 16:37:33 +00:00
inlineasm-16.ll [AMDGPU] Inline asm - added i16, half and i128 types support 2018-06-08 16:29:04 +00:00
inlineasm-illegal-type.ll [AMDGPU] Inline asm - added i16, half and i128 types support 2018-06-08 16:29:04 +00:00
inlineasm-packed.ll AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
input-mods.ll
insert-skip-from-vcc.mir [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
insert-skips-flat-vmem.mir AMDGPU: Fix MIR test verifier error 2019-06-07 17:55:07 +00:00
insert-skips-gws.mir Reapply "AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics" 2019-06-19 19:55:27 +00:00
insert-skips-ignored-insts.mir AMDGPU: Don't count mask branch pseudo towards skip threshold 2019-06-07 00:14:55 +00:00
insert-skips-kill-uncond.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
insert-subvector-unused-scratch.ll [AMDGPU] Custom lower INSERT_SUBVECTOR v3, v4, v5, v8 2019-07-04 17:38:24 +00:00
insert-waitcnts-callee.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
insert-waitcnts-exp.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
insert_subreg.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
insert_vector_dynelt.ll [AMDGPU] Fix for vector element insertion 2019-02-01 16:51:09 +00:00
insert_vector_elt.ll [AMDGPU] Regenerate tests. 2019-07-27 14:32:23 +00:00
insert_vector_elt.v2i16.ll [AMDGPU] Regenerate v2i16 insertelement tests. 2019-07-29 09:47:07 +00:00
insert_vector_elt.v2i16.subtest-nosaddr.ll [AMDGPU] Fix for vector element insertion 2019-02-01 16:51:09 +00:00
insert_vector_elt.v2i16.subtest-saddr.ll [AMDGPU] Fix for vector element insertion 2019-02-01 16:51:09 +00:00
inserted-wait-states.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
internalize.ll AMDGPU: Stop forcing internalize at -O0 2018-08-31 06:02:36 +00:00
invalid-addrspacecast.ll AMDGPU: Stop reporting is-noop addrspacecast for constant 32-bit 2018-09-10 11:59:27 +00:00
invalid-alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
invariant-load-no-alias-store.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
invert-br-undef-vcc.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
ipra-regmask.ll [AMDGPU] gfx908 register file changes 2019-07-09 19:41:51 +00:00
ipra.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
jump-address.ll [AMDGPU] change test to avoid NaN math 2018-03-19 19:26:22 +00:00
kcache-fold.ll
kernarg-stack-alignment.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
kernel-args.ll [AMDGPU] Prepare for introduction of v3 and v5 MVTs 2019-03-17 21:04:16 +00:00
kernel-argument-dag-lowering.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
known-never-nan.ll DAG: Handle extract_vector_elt in isKnownNeverNaN 2018-09-03 14:01:03 +00:00
known-never-snan.ll AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
knownbits-recursion.ll
large-alloca-compute.ll [AMDGPU] gfx1010 tests. NFC. 2019-05-13 19:30:06 +00:00
large-alloca-graphics.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
large-constant-initializer.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
large-work-group-promote-alloca.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
lcssa-optnone.ll [AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs. 2019-07-25 14:50:18 +00:00
lds-alignment.ll [NFC] fix trivial typos in comments and documents 2018-01-29 05:17:03 +00:00
lds-bounds.ll AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI 2018-10-17 15:37:48 +00:00
lds-branch-vmem-hazard.mir AMDGPU] gfx1010 hazard recognizer 2019-05-04 04:30:57 +00:00
lds-global-non-entry-func.ll AMDGPU: Error on LDS global address in functions 2018-06-08 08:05:54 +00:00
lds-initializer.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
lds-m0-init-in-loop.ll
lds-misaligned-bug.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
lds-oqap-crash.ll
lds-output-queue.ll [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
lds-relocs.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
lds-size.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
lds-zero-initializer.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
lds_atomic_f32.ll [AMDGPU] fix LDS f32 intrinsics 2018-01-26 11:09:38 +00:00
legalize-fp-load-invariant.ll [AMDGPU] Rename pass "isel" to "amdgpu-isel" 2018-10-03 03:38:22 +00:00
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
lit.local.cfg
literals.ll
liveness.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.dec.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
llvm.amdgcn.atomic.fadd.ll [AMDGPU] gfx908 atomic fadd and atomic pk_fadd 2019-07-11 00:10:17 +00:00
llvm.amdgcn.atomic.inc.ll [SelectionDAG] Propagate alias metadata to target intrinsic nodes 2019-07-03 14:33:29 +00:00
llvm.amdgcn.buffer.atomic.ll [AMDGPU] Add support for 64 bit buffer atomic artihmetic instructions 2019-03-06 17:02:06 +00:00
llvm.amdgcn.buffer.load.dwordx3.ll [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics 2019-03-22 14:58:02 +00:00
llvm.amdgcn.buffer.load.format.d16.ll AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature. 2018-02-01 18:41:33 +00:00
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll AMDGPU: Fold frame index into MUBUF 2019-06-24 14:53:56 +00:00
llvm.amdgcn.buffer.store.dwordx3.ll [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics 2019-03-22 14:58:02 +00:00
llvm.amdgcn.buffer.store.format.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.buffer.store.format.ll [AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account. 2018-04-26 16:11:19 +00:00
llvm.amdgcn.buffer.store.ll [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics 2019-03-19 16:07:00 +00:00
llvm.amdgcn.buffer.wbinvl1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.sc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.vol.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.class.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.class.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pk.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pkrtz.ll [AMDGPU] Regenerate test file for upcoming patch. NFCI. 2019-07-19 15:43:56 +00:00
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.div.fixup.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.div.fixup.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.div.fmas.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
llvm.amdgcn.div.scale.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
llvm.amdgcn.ds.append.ll AMDGPU: Fix dropping memref for ds append/consume 2019-06-14 21:01:24 +00:00
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.consume.ll AMDGPU: Fix dropping memref for ds append/consume 2019-06-14 21:01:24 +00:00
llvm.amdgcn.ds.gws.barrier.ll AMDGPU: Remove v0 workaround for DS_GWS_* instructions 2019-08-01 18:41:32 +00:00
llvm.amdgcn.ds.gws.init.ll AMDGPU: Remove v0 workaround for DS_GWS_* instructions 2019-08-01 18:41:32 +00:00
llvm.amdgcn.ds.gws.sema.br.ll AMDGPU: Don't rely on m0 being -1 for GWS offsets 2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.p.ll AMDGPU: Don't rely on m0 being -1 for GWS offsets 2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.release.all.ll AMDGPU: Don't rely on m0 being -1 for GWS offsets 2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.v.ll AMDGPU: Don't rely on m0 being -1 for GWS offsets 2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.ordered.add.gfx10.ll AMDGPU/GFX10: implement ds_ordered_count changes 2019-07-01 17:17:52 +00:00
llvm.amdgcn.ds.ordered.add.ll AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap 2019-01-16 15:43:53 +00:00
llvm.amdgcn.ds.ordered.swap.ll Reapply "AMDGPU: Split block for si_end_cf" 2019-08-01 01:25:27 +00:00
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
llvm.amdgcn.exp.ll AMDGPU: Force skip over s_sendmsg and exp instructions 2018-07-30 09:23:59 +00:00
llvm.amdgcn.exp.prim.ll [AMDGPU] gfx1010 exp modifications 2019-05-08 21:23:37 +00:00
llvm.amdgcn.fcmp.ll IR: Add immarg attribute 2019-03-12 21:02:54 +00:00
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.fmad.ftz.f16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmad.ftz.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmed3.f16.ll AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 2017-12-08 20:52:28 +00:00
llvm.amdgcn.fmed3.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
llvm.amdgcn.icmp.ll IR: Add immarg attribute 2019-03-12 21:02:54 +00:00
llvm.amdgcn.image.a16.dim.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.atomic.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.d16.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.dim.ll [AMDGPU] gfx1010 GCNNSAReassign pass 2019-05-01 16:40:49 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll [AMDGPU] Add support for a16 modifiear for gfx9 2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.gather4.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.gather4.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.getlod.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.load.a16.d16.ll [AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try 2019-01-14 11:55:24 +00:00
llvm.amdgcn.image.load.a16.ll [AMDGPU] Use three- and five-dword result type in image ops 2019-03-22 15:21:11 +00:00
llvm.amdgcn.image.nsa.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.sample.a16.dim.ll [AMDGPU] Add support for a16 modifiear for gfx9 2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.sample.d16.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.sample.dim.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.sample.ltolz.ll [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero 2018-08-01 12:12:01 +00:00
llvm.amdgcn.image.sample.o.dim.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.store.a16.d16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.store.a16.ll [AMDGPU] support image load/store a16 2018-10-31 10:34:48 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicit.buffer.ptr.ll AMDGPU: Revert accidental change to test 2019-07-01 19:09:57 +00:00
llvm.amdgcn.implicitarg.ptr.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
llvm.amdgcn.init.exec.ll AMDGPU: Fix a corner case crash in SIOptimizeExecMasking 2018-04-23 13:05:50 +00:00
llvm.amdgcn.interp.f16.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
llvm.amdgcn.interp.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.kill.ll [AMDGPU] more gfx1010 tests. NFC. 2019-06-12 18:44:11 +00:00
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll AMDGPU: Fix tests using old number for constant address space 2018-09-10 02:54:25 +00:00
llvm.amdgcn.mfma.ll [AMDGPU] use v32f32 for 3 mfma intrinsics 2019-07-12 22:42:01 +00:00
llvm.amdgcn.mov.dpp.ll [AMDGPU] gfx1010 dpp16 and dpp8 2019-06-12 18:02:41 +00:00
llvm.amdgcn.mov.dpp8.ll [AMDGPU] gfx1010 dpp16 and dpp8 2019-06-12 18:02:41 +00:00
llvm.amdgcn.mqsad.pk.u16.u8.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.mul.i24.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
llvm.amdgcn.mul.u24.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
llvm.amdgcn.permlane.ll [AMDGPU] gfx1010 premlane instructions 2019-06-12 17:52:51 +00:00
llvm.amdgcn.ps.live.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
llvm.amdgcn.qsad.pk.u16.u8.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
llvm.amdgcn.queue.ptr.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.raw.buffer.atomic.ll AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec} 2019-08-05 09:36:06 +00:00
llvm.amdgcn.raw.buffer.load.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.ll [AMDGPU] gfx1010 tests. NFC. 2019-05-08 23:31:32 +00:00
llvm.amdgcn.raw.buffer.store.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.ll AMDGPU: Correct behavior of f16/i16 non-format store intrinsics 2019-08-05 14:57:59 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.raw.tbuffer.load.ll [AMDGPU] gfx1010 tests. NFC. 2019-05-08 23:31:32 +00:00
llvm.amdgcn.raw.tbuffer.store.d16.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.raw.tbuffer.store.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll AMDGPU: Fold frame index into MUBUF 2019-06-24 14:53:56 +00:00
llvm.amdgcn.readlane.ll AMDGPU: Fold readlane from copy of SGPR or imm 2019-06-18 12:23:46 +00:00
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll [DAGCombine][X86][AArch64][AMDGPU] (x - y) + -1 -> add (xor y, -1), x fold. Try 3 2019-05-30 20:37:29 +00:00
llvm.amdgcn.s.buffer.load.ll Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg 2019-04-10 18:00:41 +00:00
llvm.amdgcn.s.dcache.inv.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.inv.vol.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.vol.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.get.waveid.in.workgroup.ll [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll AMDGPU: s_waitcnt field should be treated as unsigned 2019-07-11 23:42:57 +00:00
llvm.amdgcn.sad.hi.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u8.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u16.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.amdgcn.sbfe.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
llvm.amdgcn.sdot2.ll [AMDGPU] gfx908 dot instruction support 2019-07-11 00:00:27 +00:00
llvm.amdgcn.sdot4.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.sdot8.ll [AMDGPU] gfx908 dot instruction support 2019-07-11 00:00:27 +00:00
llvm.amdgcn.sendmsg.ll [AMDGPU][MC] Enabled constant expressions as operands of sendmsg 2019-06-28 14:14:02 +00:00
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.softwqm.ll [AMDGPU] Add llvm.amdgcn.softwqm intrinsic 2019-07-26 09:54:12 +00:00
llvm.amdgcn.struct.buffer.atomic.ll AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec} 2019-08-05 09:36:06 +00:00
llvm.amdgcn.struct.buffer.load.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.ll [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics 2019-03-19 16:07:00 +00:00
llvm.amdgcn.struct.buffer.store.format.d16.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.format.ll [AMDGPU] New buffer intrinsics 2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.ll AMDGPU: Correct behavior of f16/i16 non-format store intrinsics 2019-08-05 14:57:59 +00:00
llvm.amdgcn.struct.tbuffer.load.d16.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.struct.tbuffer.load.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.struct.tbuffer.store.d16.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.struct.tbuffer.store.ll [AMDGPU] gfx1010 MIMG implementation 2019-05-01 16:32:58 +00:00
llvm.amdgcn.tbuffer.load.d16.ll AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature. 2018-02-01 18:41:33 +00:00
llvm.amdgcn.tbuffer.load.dwordx3.ll [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics 2019-03-22 14:58:02 +00:00
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.amdgcn.tbuffer.store.dwordx3.ll [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics 2019-03-22 14:58:02 +00:00
llvm.amdgcn.tbuffer.store.ll [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll UpdateTestChecks: fix AMDGPU handling 2019-05-18 13:00:03 +00:00
llvm.amdgcn.udot2.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.udot4.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.udot8.ll [AMDGPU] gfx1011/gfx1012 targets 2019-06-14 00:33:31 +00:00
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll [AMDGPU] gfx1010 dpp16 and dpp8 2019-06-12 18:02:41 +00:00
llvm.amdgcn.wave.barrier.ll AMDGPU: wave_barrier is not isBarrier 2019-03-27 15:54:45 +00:00
llvm.amdgcn.wavefrontsize.ll [AMDGPU] gfx1010 wavefrontsize intrinsic folding 2019-06-17 17:57:50 +00:00
llvm.amdgcn.workgroup.id.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.workitem.id.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
llvm.amdgcn.wqm.vote.ll AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
llvm.amdgcn.writelane.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
llvm.ceil.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.cos.f16.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.cos.ll
llvm.dbg.value.ll [DebugInfo] Stop changing labels for register-described parameter DBG_VALUEs 2019-02-13 09:34:07 +00:00
llvm.exp2.f16.ll [AMDGPU] Fixed some instructions latencies 2018-03-30 16:19:13 +00:00
llvm.exp2.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
llvm.floor.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.fma.f16.ll [AMDGPU] Enable v4f16 and above for v_pk_fma instructions 2019-07-29 08:15:10 +00:00
llvm.fmuladd.f16.ll [AMDGPU] gfx1010: use fmac instructions 2019-05-04 04:20:37 +00:00
llvm.log.f16.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
llvm.log.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.log2.f16.ll
llvm.log2.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
llvm.log10.f16.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
llvm.log10.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
llvm.maxnum.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
llvm.memcpy.ll AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0 2019-06-16 17:32:01 +00:00
llvm.minnum.f16.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
llvm.pow.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.sin.f16.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.sin.ll [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
llvm.sqrt.f16.ll [AMDGPU] Fixed some instructions latencies 2018-03-30 16:19:13 +00:00
llvm.trunc.f16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-constant-f32.ll [AMDGPU] Increased vector length for global/constant loads. 2018-03-07 17:09:18 +00:00
load-constant-f64.ll [AMDGPU] Increased vector length for global/constant loads. 2018-03-07 17:09:18 +00:00
load-constant-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-constant-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-constant-i16.ll [LegalizeVectorTypes] Allow single loads and stores for more short vectors 2019-03-27 20:35:56 +00:00
load-constant-i32.ll [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
load-constant-i64.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
load-global-f32.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
load-global-f64.ll
load-global-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-global-i8.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
load-global-i16.ll [LegalizeVectorTypes] Allow single loads and stores for more short vectors 2019-03-27 20:35:56 +00:00
load-global-i32.ll [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
load-global-i64.ll
load-hi16.ll AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
load-input-fold.ll
load-lo16.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
load-local-f32-no-ds128.ll AMDGPU: Add a missing test for the 128-bit local addr space option 2018-05-15 21:41:57 +00:00
load-local-f32.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-local-f64.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-local-i1.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-local-i8.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
load-local-i16.ll [LegalizeVectorTypes] Allow single loads and stores for more short vectors 2019-03-27 20:35:56 +00:00
load-local-i32.ll [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
load-local-i64.ll AMDGPU: enable 128-bit for local addr space under an option 2018-04-10 22:48:23 +00:00
load-select-ptr.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
load-weird-sizes.ll
local-64.ll [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
local-atomics-fp.ll AMDGPU: Add support for cross address space synchronization scopes 2019-03-25 20:50:21 +00:00
local-atomics.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
local-atomics64.ll Allow FP types for atomicrmw xchg 2019-01-17 10:49:01 +00:00
local-memory.amdgcn.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
local-memory.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
local-memory.r600.ll
local-stack-slot-offset.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
loop-address.ll
loop-idiom.ll AMDGPU: Fix tests using the default alloca address space 2019-07-01 15:23:03 +00:00
loop_break.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
loop_exit_with_xor.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
lower-kernargs.ll AMDGPU: Partially fix default device for HSA 2019-03-17 21:31:35 +00:00
lower-mem-intrinsics.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll AMDGPU: Don't use the default cpu in a few tests 2019-04-03 00:00:58 +00:00
lshr.v2i16.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
macro-fusion-cluster-vcc-uses.mir [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic 2019-03-18 19:35:44 +00:00
mad-combine.ll AMDGPU: Fix -enable-var-scope violations 2017-11-12 23:53:44 +00:00
mad-mix-hi.ll AMDGPU: Remove custom BUILD_VECTOR combine 2018-10-30 01:37:59 +00:00
mad-mix-lo.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
mad-mix.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
mad.u16.ll [AMDGPU] gfx1010 lost VOP2 forms of some add/sub 2019-05-02 04:26:35 +00:00
mad24-get-global-id.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
mad_64_32.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
mad_int24.ll
mad_uint24.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
madak-inline-constant.mir [AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32. 2018-09-10 16:42:49 +00:00
madak.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
madmk.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
mai-hazards.mir [AMDGPU] gfx908 hazard recognizer 2019-07-11 21:30:34 +00:00
mai-inline.ll [AMDGPU] gfx908 mfma support 2019-07-11 21:19:33 +00:00
max-literals.ll
max-sgprs.ll [AMDGPU] gfx1010 VOP2 changes 2019-04-26 16:37:51 +00:00
max.i16.ll [AMDGPU] Regenerate some f16/i16 tests. 2019-03-17 20:36:12 +00:00
max.ll AMDGPU: Don't use the default cpu in a few tests 2019-04-03 00:00:58 +00:00
max3.ll [AMDGPU] Ban i8 min3 promotion. 2019-03-19 15:50:24 +00:00
med3-no-simplify.ll Reapply [ValueTracking] Support min/max selects in computeConstantRange() 2019-04-07 17:22:16 +00:00
mem-builtins.ll [AMDGPU] Mark test functions with hidden visibility 2019-02-01 21:23:28 +00:00
memory-legalizer-amdpal.ll AMDGPU: Add support for cross address space synchronization scopes 2019-03-25 20:50:21 +00:00
memory-legalizer-atomic-cmpxchg.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-atomic-fence.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-atomic-insert-end.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
memory-legalizer-atomic-rmw.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-invalid-addrspace.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
memory-legalizer-invalid-syncscope.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-load.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory-legalizer-local.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
memory-legalizer-mesa3d.ll AMDGPU: Add support for cross address space synchronization scopes 2019-03-25 20:50:21 +00:00
memory-legalizer-multiple-mem-operands-atomics.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
memory-legalizer-region.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
memory-legalizer-store-infinite-loop.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
memory-legalizer-store.ll [AMDGPU] gfx1010 memory legalizer 2019-05-06 21:57:02 +00:00
memory_clause.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
memory_clause.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
merge-load-store-physreg.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
merge-load-store-vreg.mir [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers 2019-03-18 19:25:39 +00:00
merge-load-store.mir AMDGPU/LoadStoreOptimizer: combine MMOs when merging instructions 2019-07-29 16:40:58 +00:00
merge-m0.mir [AMDGPU] Enable merging m0 initializations. 2019-07-15 22:07:05 +00:00
merge-store-crash.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
merge-store-usedef.ll
merge-stores.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
mesa3d.ll AMDGPU: Fix not adding ImplicitBufferPtr as a live-in 2019-05-31 22:47:36 +00:00
mesa_regression.ll
min.ll [AMDGPU] gfx1010 lost VOP2 forms of some add/sub 2019-05-02 04:26:35 +00:00
min3.ll [AMDGPU] Ban i8 min3 promotion. 2019-03-19 15:50:24 +00:00
mir-print-dead-csr-fi.mir MIR: Fix printer crashing on dead CSR frame indexes 2019-05-28 13:08:31 +00:00
misched-killflags.mir MIR: Freeze reserved regs after parsing everything 2019-03-27 16:12:26 +00:00
missing-store.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mixed-wave32-wave64.ll [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
mixed_wave32_wave64.ll [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
mode-register.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
move-addr64-rsrc-dead-subreg-writes.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
movreld-bug.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
movrels-bug.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
mubuf-legalize-operands.ll AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
mubuf-legalize-operands.mir [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
mubuf-offset-private.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
mubuf-shader-vgpr.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
mubuf.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
mul.i16.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
mul.ll AMDGPU: Temporary drop s_mul_hi_i/u32 patterns 2019-05-28 21:18:34 +00:00
mul_int24.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
mul_uint24-amdgcn.ll AMDGPU: Add 24-bit mul intrinsics 2019-07-15 17:50:31 +00:00
mul_uint24-r600.ll
multi-divergent-exit-region.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
multi-dword-vgpr-spill.ll AMDGPU: Don't fix emergency stack slot at offset 0 2019-06-05 22:37:50 +00:00
multilevel-break.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
nand.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
nested-calls.ll [AMDGPU] Created a sub-register class for the return address operand in the return instruction. 2019-07-09 16:48:42 +00:00
nested-loop-conditions.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0 2019-06-16 17:32:01 +00:00
no-remat-indirect-mov.mir AMDGPU: Don't rematerialize mov with implicit operands 2019-02-04 22:26:21 +00:00
no-shrink-extloads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
noop-shader-O0.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
nop-data.ll [llvm-objdump] Tidy up AMDGCNPrettyPrinter 2019-06-18 06:35:18 +00:00
nor.ll [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
not-scalarize-volatile-load.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
nsa-reassign.ll [AMDGPU] Fix high occupancy calculation and print it 2019-07-31 01:07:10 +00:00
nsa-vmem-hazard.mir AMDGPU] gfx1010 hazard recognizer 2019-05-04 04:30:57 +00:00
nullptr.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
occupancy-levels.ll [AMDGPU] Fix high occupancy calculation and print it 2019-07-31 01:07:10 +00:00
omod-nsz-flag.mir AMDGPU: Serialize mode from MachineFunctionInfo 2019-07-10 16:09:26 +00:00
omod.ll
opencl-image-metadata.ll
operand-folding.ll
operand-spacing.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
opt-sgpr-to-vgpr-copy.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
optimize-exec-masking-pre-ra.mir AMDGPU: Forgot to commit test file for r358890 2019-05-03 13:55:40 +00:00
optimize-if-exec-masking.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
optimize-negated-cond-exec-masking-wave32.mir [AMDGPU] gfx10 tests. NFC. 2019-06-20 16:29:40 +00:00
optimize-negated-cond-exec-masking.mir [AMDGPU] Fixed addReg() in SIOptimizeExecMaskingPreRA.cpp 2019-04-23 17:59:26 +00:00
optimize-negated-cond.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
or.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
or3.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
pack.v2f16.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
pack.v2i16.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
packed-op-sel.ll AMDGPU: Select DS insts without m0 initialization 2017-11-29 00:55:57 +00:00
packetizer.ll
parallelandifcollapse.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll RegAllocFast: Leave unassigned virtreg entries in map 2018-11-07 06:57:03 +00:00
partial-shift-shrink.ll AMDGPU: Handle partial shift reduction for variable shifts 2018-05-09 20:52:54 +00:00
partially-dead-super-register-immediate.ll
peephole-opt-regseq-removal.mir [PeepholeOpt] Don't stop simplifying copies on sequence of subregs 2019-03-27 17:27:56 +00:00
pei-reg-scavenger-position.mir AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
perfhint.ll [AMDGPU] Do not consider indirect acces through phi for wave limiter 2018-06-11 16:50:49 +00:00
permute.ll [AMDGPU] Corrected computeKnownBits for V_PERM_B32 2018-06-13 18:52:54 +00:00
phi-elimination-assertion.mir [PHIElimination] Lower a PHI node with only undef uses as IMPLICIT_DEF 2018-09-30 17:26:58 +00:00
pk_max_f16_literal.ll [AMDGPU] gfx1010 allows VOP3 to have a literal 2019-05-02 04:01:39 +00:00
post-ra-sched-kill-bundle-use-inst.mir ScheduleDAG: Fix incorrectly killing registers in bundles 2019-07-05 15:32:28 +00:00
postra-norename.mir [MachineOperand][Target] MachineOperand::isRenamable semantics changes 2018-02-23 18:25:08 +00:00
power-sched-no-instr-sunit.mir [AMDGPU] fixed scheduler crash in gfx908 2019-07-15 15:34:05 +00:00
predicate-dp4.ll
predicates.ll
preserve-hi16.ll [AMDGPU] gfx1010 VOP3 and VOP3P implementation 2019-04-26 17:56:03 +00:00
print-mir-custom-pseudo.ll [AMDGPU] Rename pass "isel" to "amdgpu-isel" 2018-10-03 03:38:22 +00:00
private-access-no-objects.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
private-element-size.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
private-memory-atomics.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
private-memory-r600.ll AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements 2018-02-16 19:14:17 +00:00
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
promote-alloca-calling-conv.ll AMDGPU: Remove amdgpu-max-work-group-size attribute 2019-06-05 20:32:32 +00:00
promote-alloca-globals.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
promote-alloca-invariant-markers.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
promote-alloca-lifetime.ll AMDGPU: Fix iterator crash in AMDGPUPromoteAlloca 2019-06-18 12:23:44 +00:00
promote-alloca-mem-intrinsics.ll Add a 'dynamic' parameter to the objectsize intrinsic 2019-01-30 20:34:35 +00:00
promote-alloca-no-opts.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
promote-alloca-padding-size-estimate.ll AMDGPU: Enable code object v3 for AMDHSA only 2018-11-15 02:32:43 +00:00
promote-alloca-stored-pointer-value.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
promote-alloca-to-lds-icmp.ll AMDGPU: Add an option -disable-promote-alloca-to-lds 2018-11-06 21:28:17 +00:00
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll AMDGPU: Fix using old address spaces in some tests 2018-12-05 17:34:59 +00:00
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
promote-alloca-volatile.ll
promote-constOffset-to-imm.ll [AMDGPU] Promote constant offset to the immediate by finding a new base with 13bit constant offset from the nearby instructions. 2018-12-14 21:13:14 +00:00
promote-constOffset-to-imm.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
propagate-attributes-bitcast-function.ll [AMDGPU] Propagate function attributes thru bitcasts 2019-06-17 20:42:48 +00:00
propagate-attributes-clone.ll [AMDGPU] Pass to propagate ABI attributes from kernels to the functions 2019-06-17 17:47:28 +00:00
propagate-attributes-single-set.ll [AMDGPU] Pass to propagate ABI attributes from kernels to the functions 2019-06-17 17:47:28 +00:00
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.add.ll AMDGPU: Select VOP3 form of add 2019-05-08 22:09:57 +00:00
r600.alu-limits.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
r600.amdgpu-alias-analysis.ll [AMDGPU] Add an experimental buffer fat pointer address space. 2019-03-18 14:44:28 +00:00
r600.bitcast.ll
r600.extract-lowbits.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
r600.func-alignment.ll AMDGPU/R600: Make sure functions are cacheline aligned 2018-05-31 04:08:08 +00:00
r600.global_atomics.ll
r600.private-memory.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
r600.sub.ll AMDGPU: Select VOP3 form of sub 2019-05-03 15:37:07 +00:00
r600.work-item-intrinsics.ll AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS 2018-08-01 18:36:07 +00:00
r600cfg.ll
rcp-pattern.ll
rcp_iflag.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
read_register.ll
readcyclecounter.ll [AMDGPU] Always use s_memtime for readcyclecounter 2019-07-09 03:10:18 +00:00
readlane_exec0.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
reassoc-scalar.ll [AMDGPU] Fixed hang during DAG combine 2019-02-26 20:56:25 +00:00
reduce-build-vec-ext-to-ext-build-vec.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
reduce-load-width-alignment.ll
reduce-saveexec.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
reduce-store-width-alignment.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
reduction.ll DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
reg-coalescer-sched-crash.ll
regbank-reassign.mir [AMDGPU] Fixed occupancy calculation for gfx10 2019-07-19 21:29:51 +00:00
regcoal-subrange-join-seg.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
regcoal-subrange-join.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
regcoalesce-cannot-join-failures.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
regcoalesce-dbg.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
regcoalesce-prune.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
regcoalescing-remove-partial-redundancy-assert.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
register-count-comments.ll
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
rename-independent-subregs.mir RenameIndependentSubregs: Fix handling of undef tied operands 2018-07-09 20:07:03 +00:00
reorder-stores.ll
reqd-work-group-size.ll AMDGPU: Add pass to optimize reqd_work_group_size 2018-05-18 21:35:00 +00:00
ret.ll AMDGPU/GlobalISel: Handle most function return types 2019-07-26 02:36:05 +00:00
ret_jump.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
returnaddress.ll AMDGPU: Return address lowering 2019-05-29 18:20:11 +00:00
rewrite-out-arguments-address-space.ll IR: print value numbers for unnamed function arguments 2019-08-03 14:28:34 +00:00
rewrite-out-arguments.ll IR: print value numbers for unnamed function arguments 2019-08-03 14:28:34 +00:00
rotl.i64.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
rotl.ll
rotr.i64.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
rotr.ll
rsq.ll
rv7x0_count3.ll
s_addk_i32.ll AMDGPU: Explicitly define a triple for some tests 2019-06-17 19:25:57 +00:00
s_code_end.ll [AMDGPU] Increase kernel padding 2019-07-24 19:40:13 +00:00
s_movk_i32.ll
s_mulk_i32.ll AMDGPU: Explicitly define a triple for some tests 2019-06-17 19:25:57 +00:00
sad.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
saddo.ll [AMDGPU] Regenerated saddo.ll test file for D47927 2019-08-02 17:52:55 +00:00
salu-to-valu.ll [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting 2019-06-17 10:54:12 +00:00
sampler-resource-id.ll
scalar-branch-missing-and-exec.ll AMDGPU: Bring processors and features in sync with the spec 2018-02-16 21:26:25 +00:00
scalar-store-cache-flush.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
scalar_to_vector.ll [AMDGPU] Regenerate tests. 2019-07-27 14:32:23 +00:00
scalar_to_vector_v2x16.ll [AMDGPU] Restored selection of scalar_to_vector (v2x16) 2018-11-19 19:58:13 +00:00
sched-assert-onlydbg-value-empty-region.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sched-crash-dbg-value.mir AMDGPU: Correct properties for adjcallstack* pseudos 2019-07-01 22:01:05 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental) 2017-11-20 14:35:53 +00:00
schedule-kernel-arg-loads.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit.ll
schedule-regpressure-limit2.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
schedule-regpressure-limit3.ll [AMDGPU] Fix amdgpu-waves-per-eu accounting in scheduler 2018-05-12 01:41:56 +00:00
schedule-regpressure.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
schedule-vs-if-nested-loop-failure.ll [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
schedule-vs-if-nested-loop.ll
scheduler-handle-move-bundle.mir LiveIntervals: Fix handleMove asserting on BUNDLE 2019-07-19 19:32:00 +00:00
scheduler-subrange-crash.ll AMDGPU: Convert tests away from llvm.SI.load.const 2019-01-17 22:47:26 +00:00
scratch-buffer.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
scratch-simple.ll AMDGPU/GFX10: fix scratch resource descriptor 2019-07-01 15:43:00 +00:00
sdiv.ll [TargetLowering] Add SimplifyMultipleUseDemandedBits 2019-07-23 12:39:08 +00:00
sdivrem24.ll [AMDGPU] Convert rcp to rcp_iflag 2018-06-27 15:33:33 +00:00
sdivrem64.ll
sdwa-gfx9.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sdwa-op64-test.ll [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos 2018-12-03 13:04:54 +00:00
sdwa-ops.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sdwa-peephole-instr-gfx10.mir [AMDGPU] gfx1010: use fmac instructions 2019-05-04 04:20:37 +00:00
sdwa-peephole-instr.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sdwa-peephole.ll [AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32 2019-05-06 22:27:05 +00:00
sdwa-preserve.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sdwa-scalar-ops.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
sdwa-vop2-64bit.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll [AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32 2019-07-10 14:53:47 +00:00
select-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
select-opt.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
select-undef.ll Moved dag-combine-select-undef.ll into amdgpu. NFC. 2018-11-17 00:17:15 +00:00
select-vectors.ll [AMDGPU] Added v5i32 and v5f32 register classes 2019-03-22 10:11:21 +00:00
select.f16.ll [AMDGPU] Regenerate some f16/i16 tests. 2019-03-17 20:36:12 +00:00
select.ll
select64.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
sendmsg-m0-hazard.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
set-dx10.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll Check shouldReduceLoadWidth from SimplifySetCC 2018-10-31 21:24:30 +00:00
setcc-opt.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
setcc-sext.ll
setcc.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
setcc64.ll
seto.ll
setuo.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
sgpr-control-flow.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
sgpr-copy-duplicate-operand.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
sgpr-copy.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
sgpr-limit.ll [AMDGPU] Increases available SGPR for Calling Convention 2019-05-15 14:43:55 +00:00
sgpr-spill-wrong-stack-id.mir AMDGPU: Correct properties for adjcallstack* pseudos 2019-07-01 22:01:05 +00:00
sgprcopies.ll
shader-addr64-nonuniform.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
shared-op-cycle.ll
shift-and-i64-ubfe.ll [DAGCombine] Prune unnused nodes. 2019-03-29 17:35:56 +00:00
shift-and-i128-ubfe.ll
shift-i64-opts.ll [DAGCombine] Prune unnused nodes. 2019-03-29 17:35:56 +00:00
shift-i128.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
shl-add-to-add-shl.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
shl.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
shl.v2i16.ll [AMDGPU] Divergence driven instruction selection. Part 1. 2018-09-21 10:31:22 +00:00
shl_add.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
shl_add_constant.ll [DAG] Refactor DAGCombiner::ReassociateOps 2019-04-29 17:50:10 +00:00
shl_add_ptr.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
shl_or.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
shrink-add-sub-constant.ll AMDGPU: Treat undef as an inline immediate 2019-06-20 16:01:09 +00:00
shrink-carry.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
shrink-vop3-carry-out.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
si-annotate-cf.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
si-annotate-cfg-loop-assert.ll
si-annotatecfg-multiple-backedges.ll [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
si-fix-sgpr-copies.mir [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
si-instr-info-correct-implicit-operands.ll Rename ExpandISelPseudo->FinalizeISel, delay register reservation 2019-06-19 00:25:39 +00:00
si-lower-control-flow-kill.ll AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic 2018-04-24 21:37:57 +00:00
si-lower-control-flow-unreachable-block.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
si-lower-control-flow.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
si-lower-i1-copies.mir AMDGPU: Fix LCSSA phi lowering in SILowerI1Copies 2019-04-23 13:12:52 +00:00
si-lower-sgpr-spills.mir [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass 2019-07-19 18:50:53 +00:00
si-scheduler.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
si-sgpr-spill.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
si-spill-cf.ll AMDGPU: Convert tests away from llvm.SI.load.const 2019-01-17 22:47:26 +00:00
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
si-vector-hang.ll
sibling-call.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
sign_extend.ll AMDGPU: Don't use the default cpu in a few tests 2019-04-03 00:00:58 +00:00
simplify-libcalls.ll [AMDGPU] Fix discarded result of addAttribute 2018-12-09 21:56:50 +00:00
simplifydemandedbits-recursion.ll Use the return value of UpdateNodeOperands(); in some cases, UpdateNodeOperands() modifies the node in-place and using the return value isn’t strictly necessary. However, it does not necessarily modify the node, but may return a resultant node if it already exists in the DAG. See comments in UpdateNodeOperands(). In that case, the return value must be used to avoid such scenarios as an infinite loop (node is assumed to have been updated, so added back to the worklist, and re-processed; however, node hasn’t changed so it is once again passed to UpdateNodeOperands(), assumed modified, added back to worklist; cycle infinitely repeats). 2017-10-16 23:38:53 +00:00
sint_to_fp.f64.ll
sint_to_fp.i64.ll [AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32 2019-07-10 14:53:47 +00:00
sint_to_fp.ll
sitofp.f16.ll [AMDGPU] Add instruction selection for i1 to f16 conversion 2018-09-19 16:32:12 +00:00
skip-branch-taildup-ret.mir AMDGPU: Insert skip branches over return blocks 2019-06-06 22:51:51 +00:00
skip-branch-trap.ll AMDGPU: Force skips around traps 2019-06-07 23:02:52 +00:00
skip-if-dead.ll AMDGPU: Force skip over SMRD, VMEM and s_waitcnt instructions 2019-04-17 16:31:52 +00:00
smed3.ll Reapply [ValueTracking] Support min/max selects in computeConstantRange() 2019-04-07 17:22:16 +00:00
smem-no-clause-coalesced.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
smem-war-hazard.mir [AMDGPU] more gfx1010 tests. NFC. 2019-06-12 18:44:11 +00:00
sminmax.ll [AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32 2019-05-06 22:27:05 +00:00
sminmax.v2i16.ll AMDGPU: Undo sub x, c canonicalization for v2i16 2019-06-19 23:37:43 +00:00
smrd-fold-offset.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
smrd-gfx10.ll AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsic 2019-06-16 17:14:12 +00:00
smrd-vccz-bug.ll AMDGPU/InsertWaitcnts: Untangle some semi-global state 2018-11-29 11:06:06 +00:00
smrd.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
sopk-compares.ll AMDGPU: Explicitly define a triple for some tests 2019-06-17 19:25:57 +00:00
sp-too-many-input-sgprs.ll AMDGPU: Invert frame index offset interpretation 2019-06-05 22:20:47 +00:00
spill-agpr.ll [AMDGPU] use v32f32 for 3 mfma intrinsics 2019-07-12 22:42:01 +00:00
spill-alloc-sgpr-init-bug.ll AMDGPU: Fix register name format in tests 2018-03-27 18:39:42 +00:00
spill-before-exec.mir AMDGPU: Fix test failing since r365512 2019-07-09 17:54:34 +00:00
spill-cfg-position.ll AMDGPU: Assume xnack is enabled by default 2019-05-16 14:48:34 +00:00
spill-csr-frame-ptr-reg-copy.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
spill-empty-live-interval.mir AMDGPU: Invert frame index offset interpretation 2019-06-05 22:20:47 +00:00
spill-m0.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
spill-offset-calculation.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
spill-scavenge-offset.ll
spill-to-smem-m0.ll
spill-vgpr-to-agpr.ll [AMDGPU] Reserve all AGPRs on targets which do not have them 2019-07-30 19:29:33 +00:00
spill-wide-sgpr.ll [AMDGPU] Added v5i32 and v5f32 register classes 2019-03-22 10:11:21 +00:00
split-arg-dbg-value.ll AMDGPU: Attempt to fix bot error 2019-07-19 14:56:24 +00:00
split-scalar-i64-add.ll CodeGen: Make computeRegisterLiveness consider successors 2018-08-30 07:17:51 +00:00
split-smrd.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
split-vector-memoperand-offsets.ll
splitkit.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
sra.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
sram-ecc-default.ll AMDGPU: Assume ECC is enabled by default if supported 2019-04-03 01:58:57 +00:00
srem.ll [AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32 2019-05-06 22:27:05 +00:00
srl.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
ssubo.ll [CodeGen] Handle vector UADDO, SADDO, USUBO, SSUBO 2019-02-07 21:02:22 +00:00
stack-realign-kernel.ll AMDGPU: Disable stack realignment for kernels 2019-06-03 21:33:22 +00:00
stack-realign.ll AMDGPU: Make s34 the FP register 2019-07-08 19:03:38 +00:00
stack-size-overflow.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
stack-slot-color-sgpr-vgpr-spills.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
store-barrier.ll
store-global.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
store-hi16.ll AMDGPU: Always use s33 for global scratch wave offset 2019-06-20 21:58:24 +00:00
store-local.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
store-private.ll AMDGPU: Stop trying to extend arguments for clover 2018-07-28 12:34:25 +00:00
store-v3i64.ll [AMDGPU] Fix dwordx3/southern-islands failures. 2019-01-10 16:21:08 +00:00
store-vector-ptrs.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
store-weird-sizes.ll [AMDGPU] Reapplied BFE canonicalization from D60462 2019-05-08 15:49:10 +00:00
store_typed.ll
stress-calls.ll Reapply "AMDGPU: Force inlining if LDS global address is used" 2018-07-10 14:03:41 +00:00
structurize.ll
structurize1.ll
sub.i16.ll AMDGPU: Explicitly define a triple for some tests 2019-06-17 19:25:57 +00:00
sub.ll AMDGPU: Select VOP3 form of sub 2019-05-03 15:37:07 +00:00
sub.v2i16.ll [AMDGPU] Regenerate vector sub tests 2019-05-23 11:27:28 +00:00
sub_i1.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
subreg-coalescer-crash.ll AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
subreg-coalescer-undef-use.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
subreg-eliminate-dead.ll
subreg-intervals.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
subreg-split-live-in-error.mir AMDGPU: Invert frame index offset interpretation 2019-06-05 22:20:47 +00:00
subreg_interference.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
subvector-test.mir [AMDGPU] gfx1010 subvector test. NFC. 2019-06-17 21:55:06 +00:00
swizzle-export.ll
syncscopes.ll [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
tail-call-cgp.ll
tail-duplication-convergent.ll AMDGPU: Add intrinsics for DS GWS semaphore instructions 2019-06-20 21:11:42 +00:00
target-cpu.ll AMDGPU: Write LDS objects out as global symbols in code generation 2019-06-25 11:52:30 +00:00
tex-clause-antidep.ll
texture-input-merge.ll
trap.ll AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as 2018-05-29 19:09:13 +00:00
trunc-bitcast-vector.ll [AMDGPU] combine extractelement into several selects 2018-11-13 21:18:21 +00:00
trunc-cmp-constant.ll AMDGPU: Fix -enable-var-scope violations 2017-11-12 23:53:44 +00:00
trunc-combine.ll [AMDGPU] Regenerate tests. 2019-07-27 14:32:23 +00:00
trunc-store-f64-to-f16.ll
trunc-store-i1.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
trunc-store.ll
trunc-vector-store-assertion-failure.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
trunc.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
tti-unroll-prefs.ll
twoaddr-fma.mir [AMDGPU] gfx1010: use fmac instructions 2019-05-04 04:20:37 +00:00
twoaddr-mad.mir [AMDGPU] Added target to mir test. NFC. 2019-02-25 22:59:55 +00:00
uaddo.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
udiv.ll [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 2018-09-11 11:56:50 +00:00
udivrem.ll [AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32 2019-05-06 22:27:05 +00:00
udivrem24.ll [AMDGPU] V_CVT_F32_UBYTE{0,1,2,3} are full rate instructions 2019-03-08 09:03:11 +00:00
udivrem64.ll [AMDGPU] Fix SGPR fixing through SCC chaining 2019-03-15 12:42:21 +00:00
uint_to_fp.f64.ll
uint_to_fp.i64.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
uint_to_fp.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
uitofp.f16.ll [AMDGPU] Add instruction selection for i1 to f16 conversion 2018-09-19 16:32:12 +00:00
umed3.ll Reapply [ValueTracking] Support min/max selects in computeConstantRange() 2019-04-07 17:22:16 +00:00
unaligned-load-store.ll DAG: Fix expansion of unaligned FP loads and stores 2018-09-13 12:14:23 +00:00
undefined-physreg-sgpr-spill.mir [AMDGPU] Correct the setting of `FlatScratchInit`. 2019-07-04 13:29:45 +00:00
undefined-subreg-liverange.ll [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
uniform-crash.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
uniform-loop-inside-nonuniform.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
uniform-work-group-attribute-missing.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-nested-function-calls.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-prevent-attribute-propagation.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-propagate-attribute.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-recursion-test.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
uniform-work-group-test.ll AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
unify-metadata.ll
unigine-liveness-crash.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
unknown-processor.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
unpack-half.ll [SelectionDAG] Fixed f16-from-vector promotion problem 2018-01-09 21:36:25 +00:00
unroll.ll AMDGPU: Fix tests using the default alloca address space 2019-07-01 15:23:03 +00:00
unsupported-calls.ll [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
unsupported-cc.ll
update-phi.ll Update phis in AMDGPUUnifyDivergentExitNodes 2019-06-25 18:55:16 +00:00
urem.ll [AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32 2019-05-06 22:27:05 +00:00
use-sgpr-multiple-times.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
usubo.ll AMDGPU: Fix capitalized register names in asm constraints 2019-06-14 21:16:06 +00:00
v1i64-kernel-arg.ll
v1024.ll [AMDGPU] Change register type for v32 vectors 2019-07-16 20:06:00 +00:00
v_cndmask.ll [AMDGPU] Restrict v_cndmask_b32 abs/neg modifiers to f32 2019-07-12 15:02:59 +00:00
v_cvt_pk_u8_f32.ll
v_mac.ll [AMDGPU] Support for v3i32/v3f32 2019-03-21 12:01:21 +00:00
v_mac_f16.ll [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:25:49 +00:00
v_madak_f16.ll AMDGPU: Don't use the default cpu in a few tests 2019-04-03 00:00:58 +00:00
v_swap_b32.mir [AMDGPU] Add support for immediate operand for S_ENDPGM 2019-03-12 09:52:58 +00:00
valu-i1.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
vccz-corrupt-bug-workaround.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
vcmpx-exec-war-hazard.mir [AMDGPU] more gfx1010 tests. NFC. 2019-06-12 18:44:11 +00:00
vcmpx-permlane-hazard.mir [AMDGPU] gfx1010 premlane instructions 2019-06-12 17:52:51 +00:00
vector-alloca-addrspacecast.ll AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction. 2018-05-11 22:17:57 +00:00
vector-alloca-atomic.ll AMDGPU/SI: Don't promote alloca to vector for atomic load/store 2018-05-17 21:49:44 +00:00
vector-alloca.ll AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
vector-extract-insert.ll [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
vector-legalizer-divergence.ll [CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands 2018-06-04 20:19:45 +00:00
vector_shuffle.packed.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
vectorize-buffer-fat-pointer.ll [AMDGPU] Add an experimental buffer fat pointer address space. 2019-03-18 14:44:28 +00:00
vectorize-global-local.ll
verify-sop.mir AMDGPU: Verify that SOP2/SOPC instructions have at most one immediate operand 2019-05-07 09:19:09 +00:00
vertex-fetch-encoding.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
vgpr-spill-emergency-stack-slot-compute.ll [AMDGPU] Partial revert for the ba447bae74 2019-06-06 21:13:02 +00:00
vgpr-spill-emergency-stack-slot.ll AMDGPU: Drop remnants of byval support for shaders 2019-07-12 20:12:17 +00:00
vi-removed-intrinsics.ll Reapply "Adapt gcov to changes in CFE." 2018-12-06 18:44:48 +00:00
virtregrewrite-undef-identity-copy.mir AMDGPU: Correct properties for adjcallstack* pseudos 2019-07-01 22:01:05 +00:00
vmem-to-salu-hazard.mir AMDGPU/GFX10: Apply the VMEM-to-scalar-write hazard also to writes to EXEC 2019-07-17 11:22:57 +00:00
vmem-vcc-hazard.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
vop-shrink-frame-index.mir [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic 2019-03-18 19:35:44 +00:00
vop-shrink-non-ssa.mir [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic 2019-03-18 19:35:44 +00:00
vop-shrink.ll [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
vselect.ll
vselect64.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
waitcnt-back-edge-loop.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
waitcnt-debug.mir [AMDGPU] Waitcnt pass: add debug options 2018-04-25 19:21:26 +00:00
waitcnt-flat.ll [AMDGPU] Switch to the new addr space mapping by default 2018-02-02 16:07:16 +00:00
waitcnt-loop-irreducible.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
waitcnt-loop-single-basic-block.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
waitcnt-looptest.ll AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
waitcnt-no-redundant.mir [AMDGPU] Make note of existing waitcnt instrs; this is add-on work related to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up. 2018-02-19 19:19:59 +00:00
waitcnt-permute.mir [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained. 2018-04-27 17:59:15 +00:00
waitcnt-preexisting.mir [AMDGPU] gfx1010 VMEM and SMEM implementation 2019-04-30 22:08:23 +00:00
waitcnt-vscnt.ll [AMDGPU] gfx1010 wait count insertion 2019-05-03 21:53:53 +00:00
waitcnt.mir AMDGPU: Look through bundles for existing waitcnts 2019-07-03 00:30:44 +00:00
wave32.ll [AMDGPU] Fix high occupancy calculation and print it 2019-07-31 01:07:10 +00:00
wave_dispatch_regs.ll [AMDGPU] Ensure there are enough registers for wave dispatch 2018-04-11 17:18:36 +00:00
widen-smrd-loads.ll [DAG] Refactor DAGCombiner::ReassociateOps 2019-04-29 17:50:10 +00:00
widen-vselect-and-mask.ll DAG: Fix creating select with wrong condition type 2017-10-25 07:14:07 +00:00
widen_extending_scalar_loads.ll AMDGPU: Preserve metadata when widening loads 2018-06-05 19:52:56 +00:00
wqm.ll [MBP] Move a latch block with conditional exit and multi predecessors to top of loop 2019-06-14 23:08:59 +00:00
wqm.mir [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure. 2019-04-01 15:19:52 +00:00
write-register-vgpr-into-sgpr.ll
write_register.ll
wrong-transalu-pos-fix.ll
wwm-reserved.ll AMDGPU: Decompose all values to 32-bit pieces for calling conventions 2019-07-19 13:57:44 +00:00
xfail.r600.bitcast.ll
xnor.ll [AMDGPU] Split 64-Bit XNOR to 64-Bit NOT/XOR 2018-12-01 12:27:53 +00:00
xor.ll AMDGPU: Add pass to lower kernel arguments to loads 2018-06-26 19:10:00 +00:00
xor3-i1-const.ll [AMDGPU] Fixed handling of imemdiate i1 literals 2019-05-14 16:18:00 +00:00
xor3.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
xor_add.ll [AMDGPU] gfx1010 core wave32 changes 2019-06-20 15:08:34 +00:00
zero_extend.ll AMDGPU: Don't use the default cpu in a few tests 2019-04-03 00:00:58 +00:00
zext-i64-bit-operand.ll
zext-lid.ll [AMDGPU] Packed thread ids in function call ABI 2019-06-28 01:52:13 +00:00

README

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.