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addc-adde-sube-subc.ll
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…
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align.ll
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[RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC
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2018-04-12 11:30:59 +00:00 |
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alloca.ll
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[RISCV] Expand function call to "call" pseudoinstruction
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2018-04-25 14:19:12 +00:00 |
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alu8.ll
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[RISCV] Introduce codegen patterns for instructions introduced in RV64I
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2018-11-30 09:38:44 +00:00 |
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alu16.ll
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[RISCV] Introduce codegen patterns for instructions introduced in RV64I
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2018-11-30 09:38:44 +00:00 |
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alu32.ll
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[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions
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2019-01-12 07:32:31 +00:00 |
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alu64.ll
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[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions
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2019-01-12 07:32:31 +00:00 |
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analyze-branch.ll
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[RISCV] Expand function call to "call" pseudoinstruction
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2018-04-25 14:19:12 +00:00 |
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arith-with-overflow.ll
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[RISCV] Add tests for overflow intrinsics
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2018-06-19 06:45:47 +00:00 |
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atomic-cmpxchg-flag.ll
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[RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A
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2019-03-11 21:41:22 +00:00 |
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atomic-cmpxchg.ll
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Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
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2019-01-25 20:22:49 +00:00 |
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atomic-fence.ll
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[RISCV][NFC] Add CHECK lines for atomic operations on RV64I
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2019-01-11 19:46:48 +00:00 |
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atomic-load-store.ll
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[RISCV] Add codegen support for RV64A
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2019-01-17 10:04:39 +00:00 |
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atomic-rmw.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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bare-select.ll
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[RISCV] Codegen support for RV32F floating point comparison operations
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2018-03-21 15:11:02 +00:00 |
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blockaddress.ll
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[RISCV] Peephole optimisation for load/store of global values or constant addresses
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2018-03-19 11:54:28 +00:00 |
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branch-relaxation.ll
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…
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branch.ll
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[RISCV] Expand codegen -> compression sanity checks and move to a single file
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2018-04-18 20:17:29 +00:00 |
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bswap-ctlz-cttz-ctpop.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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byval.ll
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[RISCV] Separate base from offset in lowerGlobalAddress
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2018-05-17 18:14:53 +00:00 |
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callee-saved-fpr32s.ll
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[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
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2019-03-14 08:17:44 +00:00 |
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callee-saved-fpr64s.ll
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[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
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2019-03-14 08:17:44 +00:00 |
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callee-saved-gprs.ll
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[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
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2019-03-14 08:17:44 +00:00 |
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calling-conv-ilp32-ilp32f-common.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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calling-conv-ilp32.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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calling-conv-lp64-lp64f-common.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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calling-conv-lp64-lp64f-lp64d-common.ll
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[RISCV] Add test cases for the lp64 ABI
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2019-03-12 09:26:53 +00:00 |
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calling-conv-lp64.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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calling-conv-rv32f-ilp32.ll
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Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
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2019-01-25 20:22:49 +00:00 |
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calling-conv-sext-zext.ll
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[RISCV] Expand function call to "call" pseudoinstruction
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2018-04-25 14:19:12 +00:00 |
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calls.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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compress-inline-asm.ll
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[RISCV] Tablegen-driven Instruction Compression.
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2018-04-06 21:07:05 +00:00 |
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compress.ll
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[RISCV] Add test changes missed from rL330293
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2018-04-18 20:36:12 +00:00 |
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disable-tail-calls.ll
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[RISCV] Lower the tail pseudoinstruction
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2018-05-23 22:44:08 +00:00 |
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div.ll
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[RISCV] Introduce codegen patterns for RV64M-only instructions
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2019-01-12 07:43:06 +00:00 |
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double-arith.ll
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[RISCV] Implement RV64D codegen
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2019-02-01 03:53:30 +00:00 |
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double-bitmanip-dagcombines.ll
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[RISCV] Implement RV64D codegen
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2019-02-01 03:53:30 +00:00 |
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double-br-fcmp.ll
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[RISCV] Implement RV64D codegen
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2019-02-01 03:53:30 +00:00 |
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double-calling-conv.ll
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Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
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2019-01-25 20:22:49 +00:00 |
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double-convert.ll
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[RISCV] Implement RV64D codegen
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2019-02-01 03:53:30 +00:00 |
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double-fcmp.ll
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[RISCV] Implement RV64D codegen
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2019-02-01 03:53:30 +00:00 |
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double-frem.ll
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[RISCV] Mark FREM as Expand
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2018-11-15 14:46:11 +00:00 |
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double-imm.ll
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[RISCV] Implement RV64D codegen
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2019-02-01 03:53:30 +00:00 |
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double-intrinsics.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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double-mem.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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double-previous-failure.ll
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[RISCV] Expand function call to "call" pseudoinstruction
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2018-04-25 14:19:12 +00:00 |
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double-select-fcmp.ll
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[RISCV] Implement RV64D codegen
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2019-02-01 03:53:30 +00:00 |
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double-stack-spill-restore.ll
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[RISCV] Implement RV64D codegen
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2019-02-01 03:53:30 +00:00 |
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fixups-diff.ll
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[RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true
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2018-08-16 11:26:37 +00:00 |
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fixups-relax-diff.ll
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[RISCV] Support .option relax and .option norelax
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2018-11-12 14:25:07 +00:00 |
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float-arith.ll
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[RISCV] Add RV64F codegen support
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2019-01-31 22:48:38 +00:00 |
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float-bitmanip-dagcombines.ll
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[RISCV] Add RV64F codegen support
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2019-01-31 22:48:38 +00:00 |
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float-br-fcmp.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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float-convert.ll
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[RISCV] Add RV64F codegen support
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2019-01-31 22:48:38 +00:00 |
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float-fcmp.ll
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[RISCV] Add RV64F codegen support
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2019-01-31 22:48:38 +00:00 |
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float-frem.ll
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[RISCV] Mark FREM as Expand
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2018-11-15 14:46:11 +00:00 |
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float-imm.ll
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[RISCV] Add RV64F codegen support
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2019-01-31 22:48:38 +00:00 |
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float-intrinsics.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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float-mem.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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float-select-fcmp.ll
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[RISCV] Add RV64F codegen support
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2019-01-31 22:48:38 +00:00 |
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flt-rounds.ll
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[SelectionDAG] Support result type promotion for FLT_ROUNDS_
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2018-11-30 13:18:33 +00:00 |
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fp128.ll
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[RISCV] Avoid unnecessary XOR for seteq/setne 0
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2018-11-09 14:47:36 +00:00 |
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frame.ll
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Replace "no-frame-pointer-*" function attributes with "frame-pointer"
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2019-01-14 10:55:55 +00:00 |
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frameaddr-returnaddr.ll
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[SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands
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2018-11-30 10:02:06 +00:00 |
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get-setcc-result-type.ll
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[RISCV] Avoid unnecessary XOR for seteq/setne 0
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2018-11-09 14:47:36 +00:00 |
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hoist-global-addr-base.ll
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[RISCV] Add machine function pass to merge base + offset
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2018-06-27 20:51:42 +00:00 |
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i32-icmp.ll
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[RISCV] Avoid unnecessary XOR for seteq/setne 0
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2018-11-09 14:47:36 +00:00 |
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imm-cse.ll
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[RISCV] Add imm-cse.ll test case
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2018-04-18 20:25:07 +00:00 |
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imm.ll
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Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
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2019-01-25 20:22:49 +00:00 |
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indirectbr.ll
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[RISC-V] Fix a test case to not include label names as those aren't
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2018-06-21 05:42:05 +00:00 |
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init-array.ll
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[RISCV] Use init_array instead of ctors for RISCV target, by default
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2018-03-24 18:37:19 +00:00 |
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inline-asm.ll
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[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test
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2019-02-14 13:09:54 +00:00 |
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interrupt-attr-args-error.ll
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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interrupt-attr-invalid.ll
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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interrupt-attr-nocall.ll
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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interrupt-attr-ret-error.ll
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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interrupt-attr.ll
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[RISCV] Add support for _interrupt attribute
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2018-07-26 17:49:43 +00:00 |
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jumptable.ll
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Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
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2019-01-25 20:22:49 +00:00 |
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large-stack.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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legalize-fneg.ll
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[RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068
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2019-03-13 18:25:23 +00:00 |
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lit.local.cfg
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…
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lsr-legaladdimm.ll
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[RISCV] Implement isLegalAddImmediate
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2018-04-26 13:00:37 +00:00 |
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mem.ll
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[RISCV] Separate base from offset in lowerGlobalAddress
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2018-05-17 18:14:53 +00:00 |
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mem64.ll
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[RISCV] Introduce codegen patterns for instructions introduced in RV64I
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2018-11-30 09:38:44 +00:00 |
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mul.ll
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[RISCV] Introduce codegen patterns for RV64M-only instructions
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2019-01-12 07:43:06 +00:00 |
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musttail-call.ll
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[RISCV] Lower the tail pseudoinstruction
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2018-05-23 22:44:08 +00:00 |
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option-norelax.ll
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[RISCV] Support .option relax and .option norelax
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2018-11-12 14:25:07 +00:00 |
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option-norvc.ll
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[RISCV] Support .option rvc and norvc assembler directives
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2018-05-11 17:30:28 +00:00 |
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option-relax.ll
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[RISCV] Support .option relax and .option norelax
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2018-11-12 14:25:07 +00:00 |
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option-rvc.ll
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[RISCV] Support .option rvc and norvc assembler directives
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2018-05-11 17:30:28 +00:00 |
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pr40333.ll
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[RISCV] Custom-legalise 32-bit variable shifts on RV64
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2019-01-25 05:04:00 +00:00 |
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prefetch.ll
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[SelectionDAG] Support promotion of PREFETCH operands
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2018-11-30 10:06:31 +00:00 |
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rem.ll
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[RISCV] Introduce codegen patterns for RV64M-only instructions
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2019-01-12 07:43:06 +00:00 |
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remat.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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rotl-rotr.ll
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…
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rv32i-rv64i-float-double.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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rv64d-double-convert.ll
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[RISCV] Implement RV64D codegen
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2019-02-01 03:53:30 +00:00 |
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rv64f-float-convert.ll
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[RISCV] Add RV64F codegen support
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2019-01-31 22:48:38 +00:00 |
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rv64i-exhaustive-w-insts.ll
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[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions
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2019-01-12 07:32:31 +00:00 |
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rv64i-tricky-shifts.ll
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[RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases
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2018-12-01 05:00:00 +00:00 |
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rv64m-exhaustive-w-insts.ll
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[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M
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2019-01-25 05:11:34 +00:00 |
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select-cc.ll
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…
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sext-zext-trunc.ll
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[RISCV] Introduce codegen patterns for instructions introduced in RV64I
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2018-11-30 09:38:44 +00:00 |
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shift-masked-shamt.ll
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[RISCV] Eliminate unnecessary masking of promoted shift amounts
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2018-10-12 23:18:52 +00:00 |
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shifts.ll
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[RISCV] Expand function call to "call" pseudoinstruction
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2018-04-25 14:19:12 +00:00 |
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tail-calls.ll
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[RISCV] Fixed test case failure due to r338047
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2018-07-31 00:36:28 +00:00 |
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target-abi-invalid.ll
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[RISCV] Support -target-abi at the MC layer and for codegen
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2019-03-09 09:28:06 +00:00 |
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target-abi-valid.ll
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[RISCV] Support -target-abi at the MC layer and for codegen
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2019-03-09 09:28:06 +00:00 |
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umulo-128-legalisation-lowering.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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vararg.ll
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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
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2019-03-13 16:33:45 +00:00 |
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wide-mem.ll
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[RISCV] Separate base from offset in lowerGlobalAddress
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2018-05-17 18:14:53 +00:00 |
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zext-with-load-is-free.ll
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[RISCV] Separate base from offset in lowerGlobalAddress
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2018-05-17 18:14:53 +00:00 |
d08ed38e08