forked from OSchip/llvm-project
699 lines
22 KiB
LLVM
699 lines
22 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -jump-threading -S | FileCheck %s
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; RUN: opt < %s -aa-pipeline=basic-aa -passes=jump-threading -S | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin7"
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; Test that we can thread through the block with the partially redundant load (%2).
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; rdar://6402033
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define i32 @test1(i32* %P) nounwind {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 (...) @f1() #[[ATTR0:[0-9]+]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
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; CHECK-NEXT: br i1 [[TMP1]], label [[BB1:%.*]], label [[BB1_THREAD:%.*]]
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; CHECK: bb1.thread:
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; CHECK-NEXT: store i32 42, i32* [[P:%.*]], align 4
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[DOTPR:%.*]] = load i32, i32* [[P]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOTPR]], 36
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; CHECK-NEXT: br i1 [[TMP2]], label [[BB3]], label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 (...) @f2() #[[ATTR0]]
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; CHECK-NEXT: ret i32 0
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; CHECK: bb3:
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; CHECK-NEXT: [[RES_02:%.*]] = phi i32 [ 1, [[BB1_THREAD]] ], [ 0, [[BB1]] ]
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; CHECK-NEXT: ret i32 [[RES_02]]
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;
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entry:
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%0 = tail call i32 (...) @f1() nounwind ; <i32> [#uses=1]
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%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
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br i1 %1, label %bb1, label %bb
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bb: ; preds = %entry
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store i32 42, i32* %P, align 4
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br label %bb1
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bb1: ; preds = %entry, %bb
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ] ; <i32> [#uses=2]
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%2 = load i32, i32* %P, align 4 ; <i32> [#uses=1]
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%3 = icmp sgt i32 %2, 36 ; <i1> [#uses=1]
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br i1 %3, label %bb3, label %bb2
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bb2: ; preds = %bb1
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%4 = tail call i32 (...) @f2() nounwind ; <i32> [#uses=0]
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ret i32 %res.0
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bb3: ; preds = %bb1
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ret i32 %res.0
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}
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declare i32 @f1(...)
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declare i32 @f2(...)
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;; Check that we preserve TBAA information.
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; rdar://11039258
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define i32 @test2(i32* %P) nounwind {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 (...) @f1() #[[ATTR0]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
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; CHECK-NEXT: br i1 [[TMP1]], label [[BB1:%.*]], label [[BB1_THREAD:%.*]]
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; CHECK: bb1.thread:
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; CHECK-NEXT: store i32 42, i32* [[P:%.*]], align 4, !tbaa [[TBAA0:![0-9]+]]
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[DOTPR:%.*]] = load i32, i32* [[P]], align 4, !tbaa [[TBAA0]]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOTPR]], 36
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; CHECK-NEXT: br i1 [[TMP2]], label [[BB3]], label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 (...) @f2() #[[ATTR0]]
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; CHECK-NEXT: ret i32 0
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; CHECK: bb3:
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; CHECK-NEXT: [[RES_02:%.*]] = phi i32 [ 1, [[BB1_THREAD]] ], [ 0, [[BB1]] ]
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; CHECK-NEXT: ret i32 [[RES_02]]
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;
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entry:
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%0 = tail call i32 (...) @f1() nounwind ; <i32> [#uses=1]
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%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
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br i1 %1, label %bb1, label %bb
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bb: ; preds = %entry
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store i32 42, i32* %P, align 4, !tbaa !0
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br label %bb1
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bb1: ; preds = %entry, %bb
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%2 = load i32, i32* %P, align 4, !tbaa !0
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%3 = icmp sgt i32 %2, 36
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br i1 %3, label %bb3, label %bb2
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bb2: ; preds = %bb1
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%4 = tail call i32 (...) @f2() nounwind
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ret i32 %res.0
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bb3: ; preds = %bb1
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ret i32 %res.0
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}
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define i32 @test3(i8** %x, i1 %f) {
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; Correctly thread loads of different (but compatible) types, placing bitcasts
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; as necessary in the predecessors. This is especially tricky because the same
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; predecessor ends up with two entries in the PHI node and they must share
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; a single cast.
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8** [[X:%.*]] to i32**
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; CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 8
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to i8*
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; CHECK-NEXT: br i1 [[F:%.*]], label [[IF_END57:%.*]], label [[IF_END57]]
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; CHECK: if.end57:
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; CHECK-NEXT: [[TMP3:%.*]] = phi i8* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[TMP2]], [[ENTRY]] ]
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; CHECK-NEXT: [[TOBOOL59:%.*]] = icmp eq i8* [[TMP3]], null
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; CHECK-NEXT: br i1 [[TOBOOL59]], label [[RETURN:%.*]], label [[IF_THEN60:%.*]]
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; CHECK: if.then60:
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; CHECK-NEXT: ret i32 42
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; CHECK: return:
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; CHECK-NEXT: ret i32 13
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;
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entry:
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%0 = bitcast i8** %x to i32**
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%1 = load i32*, i32** %0, align 8
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br i1 %f, label %if.end57, label %if.then56
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if.then56:
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br label %if.end57
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if.end57:
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%2 = load i8*, i8** %x, align 8
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%tobool59 = icmp eq i8* %2, null
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br i1 %tobool59, label %return, label %if.then60
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if.then60:
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ret i32 42
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return:
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ret i32 13
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}
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define i32 @test4(i32* %P) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[V0:%.*]] = tail call i32 (...) @f1()
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; CHECK-NEXT: [[V1:%.*]] = icmp eq i32 [[V0]], 0
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; CHECK-NEXT: br i1 [[V1]], label [[BB1:%.*]], label [[BB1_THREAD:%.*]]
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; CHECK: bb1.thread:
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; CHECK-NEXT: store atomic i32 42, i32* [[P:%.*]] unordered, align 4
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[V2_PR:%.*]] = load atomic i32, i32* [[P]] unordered, align 4
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; CHECK-NEXT: [[V3:%.*]] = icmp sgt i32 [[V2_PR]], 36
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; CHECK-NEXT: br i1 [[V3]], label [[BB3]], label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: [[V4:%.*]] = tail call i32 (...) @f2()
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; CHECK-NEXT: ret i32 0
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; CHECK: bb3:
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; CHECK-NEXT: [[RES_04:%.*]] = phi i32 [ 1, [[BB1_THREAD]] ], [ 0, [[BB1]] ]
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; CHECK-NEXT: ret i32 [[RES_04]]
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;
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entry:
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%v0 = tail call i32 (...) @f1()
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %bb1, label %bb
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bb:
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store atomic i32 42, i32* %P unordered, align 4
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br label %bb1
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bb1:
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%v2 = load atomic i32, i32* %P unordered, align 4
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%v3 = icmp sgt i32 %v2, 36
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br i1 %v3, label %bb3, label %bb2
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bb2:
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%v4 = tail call i32 (...) @f2()
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ret i32 %res.0
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bb3:
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ret i32 %res.0
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}
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define i32 @test5(i32* %P) {
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; Negative test
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[V0:%.*]] = tail call i32 (...) @f1()
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; CHECK-NEXT: [[V1:%.*]] = icmp eq i32 [[V0]], 0
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; CHECK-NEXT: br i1 [[V1]], label [[BB1:%.*]], label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: store atomic i32 42, i32* [[P:%.*]] release, align 4
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; CHECK-NEXT: br label [[BB1]]
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; CHECK: bb1:
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; CHECK-NEXT: [[RES_0:%.*]] = phi i32 [ 1, [[BB]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[V2:%.*]] = load atomic i32, i32* [[P]] acquire, align 4
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; CHECK-NEXT: [[V3:%.*]] = icmp sgt i32 [[V2]], 36
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; CHECK-NEXT: br i1 [[V3]], label [[BB3:%.*]], label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: [[V4:%.*]] = tail call i32 (...) @f2()
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; CHECK-NEXT: ret i32 [[RES_0]]
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; CHECK: bb3:
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; CHECK-NEXT: ret i32 [[RES_0]]
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;
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entry:
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%v0 = tail call i32 (...) @f1()
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %bb1, label %bb
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bb:
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store atomic i32 42, i32* %P release, align 4
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br label %bb1
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bb1:
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%v2 = load atomic i32, i32* %P acquire, align 4
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%v3 = icmp sgt i32 %v2, 36
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br i1 %v3, label %bb3, label %bb2
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bb2:
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%v4 = tail call i32 (...) @f2()
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ret i32 %res.0
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bb3:
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ret i32 %res.0
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}
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define i32 @test6(i32* %P) {
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; Negative test
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[V0:%.*]] = tail call i32 (...) @f1()
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; CHECK-NEXT: [[V1:%.*]] = icmp eq i32 [[V0]], 0
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; CHECK-NEXT: br i1 [[V1]], label [[BB1:%.*]], label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: store i32 42, i32* [[P:%.*]], align 4
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; CHECK-NEXT: br label [[BB1]]
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; CHECK: bb1:
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; CHECK-NEXT: [[RES_0:%.*]] = phi i32 [ 1, [[BB]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[V2:%.*]] = load atomic i32, i32* [[P]] acquire, align 4
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; CHECK-NEXT: [[V3:%.*]] = icmp sgt i32 [[V2]], 36
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; CHECK-NEXT: br i1 [[V3]], label [[BB3:%.*]], label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: [[V4:%.*]] = tail call i32 (...) @f2()
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; CHECK-NEXT: ret i32 [[RES_0]]
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; CHECK: bb3:
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; CHECK-NEXT: ret i32 [[RES_0]]
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;
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entry:
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%v0 = tail call i32 (...) @f1()
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %bb1, label %bb
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bb:
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store i32 42, i32* %P
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br label %bb1
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bb1:
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%v2 = load atomic i32, i32* %P acquire, align 4
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%v3 = icmp sgt i32 %v2, 36
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br i1 %v3, label %bb3, label %bb2
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bb2:
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%v4 = tail call i32 (...) @f2()
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ret i32 %res.0
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bb3:
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ret i32 %res.0
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}
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define i32 @test7(i32* %P) {
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; Negative test
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[V0:%.*]] = tail call i32 (...) @f1()
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; CHECK-NEXT: [[V1:%.*]] = icmp eq i32 [[V0]], 0
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; CHECK-NEXT: br i1 [[V1]], label [[BB1:%.*]], label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: br label [[BB1]]
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; CHECK: bb1:
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; CHECK-NEXT: [[RES_0:%.*]] = phi i32 [ 1, [[BB]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[V2:%.*]] = load atomic i32, i32* [[P]] acquire, align 4
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; CHECK-NEXT: [[V3:%.*]] = icmp sgt i32 [[V2]], 36
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; CHECK-NEXT: br i1 [[V3]], label [[BB3:%.*]], label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: [[V4:%.*]] = tail call i32 (...) @f2()
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; CHECK-NEXT: ret i32 [[RES_0]]
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; CHECK: bb3:
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; CHECK-NEXT: ret i32 [[RES_0]]
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;
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entry:
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%v0 = tail call i32 (...) @f1()
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %bb1, label %bb
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bb:
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%val = load i32, i32* %P
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br label %bb1
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bb1:
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%v2 = load atomic i32, i32* %P acquire, align 4
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%v3 = icmp sgt i32 %v2, 36
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br i1 %v3, label %bb3, label %bb2
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bb2:
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%v4 = tail call i32 (...) @f2()
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ret i32 %res.0
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bb3:
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ret i32 %res.0
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}
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; Make sure we merge the aliasing metadata. We keep the range metadata for the
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; first load, as it dominates the second load. Hence we can eliminate the
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; branch.
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define void @test8(i32*, i32*, i32*) {
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: ret2:
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; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[TMP0:%.*]], align 4, !range [[RNG4:![0-9]+]]
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; CHECK-NEXT: store i32 [[A]], i32* [[TMP1:%.*]], align 4
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; CHECK-NEXT: [[XXX:%.*]] = tail call i32 (...) @f1() #[[ATTR0]]
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; CHECK-NEXT: ret void
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;
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%a = load i32, i32* %0, !tbaa !0, !range !4, !alias.scope !9, !noalias !10
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%b = load i32, i32* %0, !range !5
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store i32 %a, i32* %1
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%c = icmp eq i32 %b, 8
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br i1 %c, label %ret1, label %ret2
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ret1:
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ret void
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ret2:
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%xxx = tail call i32 (...) @f1() nounwind
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ret void
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}
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; Make sure we merge/PRE aliasing metadata correctly. That means that
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; we need to remove metadata from the existing load, and add appropriate
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; metadata to the newly inserted load.
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define void @test9(i32*, i32*, i32*, i1 %c) {
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; CHECK-LABEL: @test9(
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; CHECK-NEXT: br i1 [[C:%.*]], label [[D1:%.*]], label [[D2:%.*]]
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; CHECK: d1:
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; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[TMP0:%.*]], align 4
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; CHECK-NEXT: br label [[D3:%.*]]
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; CHECK: d2:
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; CHECK-NEXT: [[XXXX:%.*]] = tail call i32 (...) @f1() #[[ATTR0]]
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; CHECK-NEXT: [[B_PR:%.*]] = load i32, i32* [[TMP0]], align 4, !tbaa [[TBAA0]]
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; CHECK-NEXT: br label [[D3]]
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; CHECK: d3:
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; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[B_PR]], [[D2]] ], [ [[A]], [[D1]] ]
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; CHECK-NEXT: [[P:%.*]] = phi i32 [ 1, [[D2]] ], [ [[A]], [[D1]] ]
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; CHECK-NEXT: store i32 [[P]], i32* [[TMP1:%.*]], align 4
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; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[B]], 8
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; CHECK-NEXT: br i1 [[C2]], label [[RET1:%.*]], label [[RET2:%.*]]
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; CHECK: ret1:
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; CHECK-NEXT: ret void
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; CHECK: ret2:
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; CHECK-NEXT: [[XXX:%.*]] = tail call i32 (...) @f1() #[[ATTR0]]
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; CHECK-NEXT: ret void
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;
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br i1 %c, label %d1, label %d2
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d1:
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%a = load i32, i32* %0, !range !4, !alias.scope !9, !noalias !10
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br label %d3
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d2:
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%xxxx = tail call i32 (...) @f1() nounwind
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br label %d3
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d3:
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%p = phi i32 [ 1, %d2 ], [ %a, %d1 ]
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%b = load i32, i32* %0, !tbaa !0
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store i32 %p, i32* %1
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%c2 = icmp eq i32 %b, 8
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br i1 %c2, label %ret1, label %ret2
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ret1:
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ret void
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ret2:
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%xxx = tail call i32 (...) @f1() nounwind
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ret void
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}
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define i32 @fn_noalias(i1 %c2,i64* noalias %P, i64* noalias %P2) {
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; CHECK-LABEL: @fn_noalias(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C2:%.*]], label [[COND2:%.*]], label [[COND1:%.*]]
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; CHECK: cond1:
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; CHECK-NEXT: [[L1:%.*]] = load i64, i64* [[P:%.*]], align 4
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; CHECK-NEXT: store i64 42, i64* [[P2:%.*]], align 4
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; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[L1]], 0
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; CHECK-NEXT: br i1 [[C]], label [[COND2_THREAD:%.*]], label [[END:%.*]]
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; CHECK: cond2.thread:
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; CHECK-NEXT: call void @fn2(i64 [[L1]])
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; CHECK-NEXT: br label [[COND3:%.*]]
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; CHECK: cond2:
|
|
; CHECK-NEXT: [[L2_PR:%.*]] = load i64, i64* [[P]], align 4
|
|
; CHECK-NEXT: call void @fn2(i64 [[L2_PR]])
|
|
; CHECK-NEXT: [[C3:%.*]] = icmp eq i64 [[L2_PR]], 0
|
|
; CHECK-NEXT: br i1 [[C3]], label [[COND3]], label [[END]]
|
|
; CHECK: cond3:
|
|
; CHECK-NEXT: [[L23:%.*]] = phi i64 [ [[L1]], [[COND2_THREAD]] ], [ [[L2_PR]], [[COND2]] ]
|
|
; CHECK-NEXT: call void @fn3(i64 [[L23]])
|
|
; CHECK-NEXT: br label [[END]]
|
|
; CHECK: end:
|
|
; CHECK-NEXT: ret i32 0
|
|
;
|
|
entry:
|
|
br i1 %c2, label %cond2, label %cond1
|
|
|
|
cond1:
|
|
%l1 = load i64, i64* %P
|
|
store i64 42, i64* %P2
|
|
%c = icmp eq i64 %l1, 0
|
|
br i1 %c, label %cond2, label %end
|
|
|
|
cond2:
|
|
%l2 = load i64, i64* %P
|
|
call void @fn2(i64 %l2)
|
|
%c3 = icmp eq i64 %l2, 0
|
|
br i1 %c3, label %cond3, label %end
|
|
|
|
cond3:
|
|
call void @fn3(i64 %l2)
|
|
br label %end
|
|
|
|
end:
|
|
ret i32 0
|
|
}
|
|
|
|
; This tests if we can thread from %sw.bb.i to %do.body.preheader.i67 through
|
|
; %sw.bb21.i. To make this happen, %l2 should be detected as a partically
|
|
; redundant load with %l3 across the store to %phase in %sw.bb21.i.
|
|
|
|
%struct.NEXT_MOVE = type { i32, i32, i32* }
|
|
@hash_move = unnamed_addr global [65 x i32] zeroinitializer, align 4
|
|
@current_move = internal global [65 x i32] zeroinitializer, align 4
|
|
@last = internal unnamed_addr global [65 x i32*] zeroinitializer, align 8
|
|
@next_status = internal unnamed_addr global [65 x %struct.NEXT_MOVE] zeroinitializer, align 8
|
|
define fastcc i32 @Search(i64 %idxprom.i, i64 %idxprom.i89, i32 %c) {
|
|
; CHECK-LABEL: @Search(
|
|
; CHECK-NEXT: cond.true282:
|
|
; CHECK-NEXT: [[ARRAYIDX185:%.*]] = getelementptr inbounds [65 x i32], [65 x i32]* @hash_move, i64 0, i64 [[IDXPROM_I:%.*]]
|
|
; CHECK-NEXT: [[ARRAYIDX307:%.*]] = getelementptr inbounds [65 x i32], [65 x i32]* @current_move, i64 0, i64 [[IDXPROM_I]]
|
|
; CHECK-NEXT: [[ARRAYIDX89:%.*]] = getelementptr inbounds [65 x i32*], [65 x i32*]* @last, i64 0, i64 [[IDXPROM_I]]
|
|
; CHECK-NEXT: [[PHASE:%.*]] = getelementptr inbounds [65 x %struct.NEXT_MOVE], [65 x %struct.NEXT_MOVE]* @next_status, i64 0, i64 [[IDXPROM_I]], i32 0
|
|
; CHECK-NEXT: switch i32 [[C:%.*]], label [[CLEANUP:%.*]] [
|
|
; CHECK-NEXT: i32 1, label [[SW_BB_I:%.*]]
|
|
; CHECK-NEXT: i32 0, label [[SW_BB21_I:%.*]]
|
|
; CHECK-NEXT: ]
|
|
; CHECK: sw.bb.i:
|
|
; CHECK-NEXT: [[CALL_I62:%.*]] = call fastcc i32* @GenerateCheckEvasions()
|
|
; CHECK-NEXT: store i32* [[CALL_I62]], i32** [[ARRAYIDX89]], align 8
|
|
; CHECK-NEXT: [[L2:%.*]] = load i32, i32* [[ARRAYIDX185]], align 4
|
|
; CHECK-NEXT: [[TOBOOL_I63:%.*]] = icmp eq i32 [[L2]], 0
|
|
; CHECK-NEXT: br i1 [[TOBOOL_I63]], label [[SW_BB21_I_THREAD:%.*]], label [[IF_THEN_I64:%.*]]
|
|
; CHECK: sw.bb21.i.thread:
|
|
; CHECK-NEXT: store i32 10, i32* [[PHASE]], align 8
|
|
; CHECK-NEXT: br label [[DO_BODY_PREHEADER_I67:%.*]]
|
|
; CHECK: if.then.i64:
|
|
; CHECK-NEXT: store i32 7, i32* [[PHASE]], align 8
|
|
; CHECK-NEXT: store i32 [[L2]], i32* [[ARRAYIDX307]], align 4
|
|
; CHECK-NEXT: [[CALL16_I:%.*]] = call fastcc i32 @ValidMove(i32 [[L2]])
|
|
; CHECK-NEXT: [[TOBOOL17_I:%.*]] = icmp eq i32 [[CALL16_I]], 0
|
|
; CHECK-NEXT: br i1 [[TOBOOL17_I]], label [[IF_ELSE_I65:%.*]], label [[CLEANUP]]
|
|
; CHECK: if.else.i65:
|
|
; CHECK-NEXT: call void @f65()
|
|
; CHECK-NEXT: br label [[SW_BB21_I]]
|
|
; CHECK: sw.bb21.i:
|
|
; CHECK-NEXT: [[L3_PR:%.*]] = load i32, i32* [[ARRAYIDX185]], align 4
|
|
; CHECK-NEXT: store i32 10, i32* [[PHASE]], align 8
|
|
; CHECK-NEXT: [[TOBOOL27_I:%.*]] = icmp eq i32 [[L3_PR]], 0
|
|
; CHECK-NEXT: br i1 [[TOBOOL27_I]], label [[DO_BODY_PREHEADER_I67]], label [[CLEANUP]]
|
|
; CHECK: do.body.preheader.i67:
|
|
; CHECK-NEXT: call void @f67()
|
|
; CHECK-NEXT: ret i32 67
|
|
; CHECK: cleanup:
|
|
; CHECK-NEXT: call void @Cleanup()
|
|
; CHECK-NEXT: ret i32 0
|
|
;
|
|
entry:
|
|
%arrayidx185 = getelementptr inbounds [65 x i32], [65 x i32]* @hash_move, i64 0, i64 %idxprom.i
|
|
%arrayidx307 = getelementptr inbounds [65 x i32], [65 x i32]* @current_move, i64 0, i64 %idxprom.i
|
|
%arrayidx89 = getelementptr inbounds [65 x i32*], [65 x i32*]* @last, i64 0, i64 %idxprom.i
|
|
%phase = getelementptr inbounds [65 x %struct.NEXT_MOVE], [65 x %struct.NEXT_MOVE]* @next_status, i64 0, i64 %idxprom.i, i32 0
|
|
br label %cond.true282
|
|
|
|
cond.true282:
|
|
switch i32 %c, label %sw.default.i [
|
|
i32 1, label %sw.bb.i
|
|
i32 0, label %sw.bb21.i
|
|
]
|
|
|
|
sw.default.i:
|
|
br label %cleanup
|
|
|
|
sw.bb.i:
|
|
%call.i62 = call fastcc i32* @GenerateCheckEvasions()
|
|
store i32* %call.i62, i32** %arrayidx89, align 8
|
|
%l2 = load i32, i32* %arrayidx185, align 4
|
|
%tobool.i63 = icmp eq i32 %l2, 0
|
|
br i1 %tobool.i63, label %sw.bb21.i, label %if.then.i64
|
|
|
|
if.then.i64: ; preds = %sw.bb.i
|
|
store i32 7, i32* %phase, align 8
|
|
store i32 %l2, i32* %arrayidx307, align 4
|
|
%call16.i = call fastcc i32 @ValidMove(i32 %l2)
|
|
%tobool17.i = icmp eq i32 %call16.i, 0
|
|
br i1 %tobool17.i, label %if.else.i65, label %cleanup
|
|
|
|
if.else.i65:
|
|
call void @f65()
|
|
br label %sw.bb21.i
|
|
|
|
sw.bb21.i:
|
|
store i32 10, i32* %phase, align 8
|
|
%l3= load i32, i32* %arrayidx185, align 4
|
|
%tobool27.i = icmp eq i32 %l3, 0
|
|
br i1 %tobool27.i, label %do.body.preheader.i67, label %cleanup
|
|
|
|
do.body.preheader.i67:
|
|
call void @f67()
|
|
ret i32 67
|
|
|
|
cleanup:
|
|
call void @Cleanup()
|
|
ret i32 0
|
|
}
|
|
|
|
declare fastcc i32* @GenerateCheckEvasions()
|
|
declare fastcc i32 @ValidMove(i32 %move)
|
|
declare void @f67()
|
|
declare void @Cleanup()
|
|
declare void @f65()
|
|
|
|
define i32 @fn_SinglePred(i1 %c2,i64* %P) {
|
|
; CHECK-LABEL: @fn_SinglePred(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: [[L1:%.*]] = load i64, i64* [[P:%.*]], align 4
|
|
; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[L1]], 0
|
|
; CHECK-NEXT: br i1 [[C]], label [[COND3:%.*]], label [[COND1:%.*]]
|
|
; CHECK: cond1:
|
|
; CHECK-NEXT: br i1 [[C2:%.*]], label [[COND2:%.*]], label [[END:%.*]]
|
|
; CHECK: cond2:
|
|
; CHECK-NEXT: [[L2:%.*]] = phi i64 [ [[L1]], [[COND1]] ]
|
|
; CHECK-NEXT: call void @fn2(i64 [[L2]])
|
|
; CHECK-NEXT: br label [[END]]
|
|
; CHECK: cond3:
|
|
; CHECK-NEXT: call void @fn2(i64 [[L1]])
|
|
; CHECK-NEXT: call void @fn3(i64 [[L1]])
|
|
; CHECK-NEXT: br label [[END]]
|
|
; CHECK: end:
|
|
; CHECK-NEXT: ret i32 0
|
|
;
|
|
|
|
entry:
|
|
%l1 = load i64, i64* %P
|
|
%c = icmp eq i64 %l1, 0
|
|
br i1 %c, label %cond2, label %cond1
|
|
|
|
cond1:
|
|
br i1 %c2, label %cond2, label %end
|
|
|
|
cond2:
|
|
%l2 = load i64, i64* %P
|
|
call void @fn2(i64 %l2)
|
|
%c3 = icmp eq i64 %l2, 0
|
|
br i1 %c3, label %cond3, label %end
|
|
|
|
cond3:
|
|
call void @fn3(i64 %l2)
|
|
br label %end
|
|
|
|
end:
|
|
ret i32 0
|
|
}
|
|
|
|
define i32 @fn_SinglePredMultihop(i1 %c1, i1 %c2,i64* %P) {
|
|
; CHECK-LABEL: @fn_SinglePredMultihop(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: [[L1:%.*]] = load i64, i64* [[P:%.*]], align 4
|
|
; CHECK-NEXT: [[C0:%.*]] = icmp eq i64 [[L1]], 0
|
|
; CHECK-NEXT: br i1 [[C0]], label [[COND3:%.*]], label [[COND0:%.*]]
|
|
; CHECK: cond0:
|
|
; CHECK-NEXT: br i1 [[C1:%.*]], label [[COND1:%.*]], label [[END:%.*]]
|
|
; CHECK: cond1:
|
|
; CHECK-NEXT: br i1 [[C2:%.*]], label [[COND2:%.*]], label [[END]]
|
|
; CHECK: cond2:
|
|
; CHECK-NEXT: [[L2:%.*]] = phi i64 [ [[L1]], [[COND1]] ]
|
|
; CHECK-NEXT: call void @fn2(i64 [[L2]])
|
|
; CHECK-NEXT: br label [[END]]
|
|
; CHECK: cond3:
|
|
; CHECK-NEXT: call void @fn2(i64 [[L1]])
|
|
; CHECK-NEXT: call void @fn3(i64 [[L1]])
|
|
; CHECK-NEXT: br label [[END]]
|
|
; CHECK: end:
|
|
; CHECK-NEXT: ret i32 0
|
|
;
|
|
|
|
entry:
|
|
%l1 = load i64, i64* %P
|
|
%c0 = icmp eq i64 %l1, 0
|
|
br i1 %c0, label %cond2, label %cond0
|
|
|
|
cond0:
|
|
br i1 %c1, label %cond1, label %end
|
|
|
|
cond1:
|
|
br i1 %c2, label %cond2, label %end
|
|
|
|
cond2:
|
|
%l2 = load i64, i64* %P
|
|
call void @fn2(i64 %l2)
|
|
%c3 = icmp eq i64 %l2, 0
|
|
br i1 %c3, label %cond3, label %end
|
|
|
|
cond3:
|
|
call void @fn3(i64 %l2)
|
|
br label %end
|
|
|
|
end:
|
|
ret i32 0
|
|
}
|
|
|
|
declare void @fn2(i64)
|
|
declare void @fn3(i64)
|
|
|
|
|
|
; Make sure we phi-translate and make the partially redundant load in
|
|
; merge fully redudant and then we can jump-thread the block with the
|
|
; store.
|
|
;
|
|
define i32 @phi_translate_partial_redundant_loads(i32, i32*, i32*) {
|
|
; CHECK-LABEL: @phi_translate_partial_redundant_loads(
|
|
; CHECK-NEXT: [[CMP0:%.*]] = icmp ne i32 [[TMP0:%.*]], 0
|
|
; CHECK-NEXT: br i1 [[CMP0]], label [[MERGE_THREAD:%.*]], label [[MERGE:%.*]]
|
|
; CHECK: merge.thread:
|
|
; CHECK-NEXT: store i32 1, i32* [[TMP1:%.*]], align 4
|
|
; CHECK-NEXT: br label [[LEFT_X:%.*]]
|
|
; CHECK: merge:
|
|
; CHECK-NEXT: [[NEWLOAD_PR:%.*]] = load i32, i32* [[TMP2:%.*]], align 4
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[NEWLOAD_PR]], 5
|
|
; CHECK-NEXT: br i1 [[CMP1]], label [[LEFT_X]], label [[RIGHT_X:%.*]]
|
|
; CHECK: left_x:
|
|
; CHECK-NEXT: ret i32 20
|
|
; CHECK: right_x:
|
|
; CHECK-NEXT: ret i32 10
|
|
;
|
|
%cmp0 = icmp ne i32 %0, 0
|
|
br i1 %cmp0, label %left, label %right
|
|
|
|
left:
|
|
store i32 1, i32* %1, align 4
|
|
br label %merge
|
|
|
|
right:
|
|
br label %merge
|
|
|
|
merge:
|
|
%phiptr = phi i32* [ %1, %left ], [ %2, %right ]
|
|
%newload = load i32, i32* %phiptr, align 4
|
|
%cmp1 = icmp slt i32 %newload, 5
|
|
br i1 %cmp1, label %left_x, label %right_x
|
|
|
|
left_x:
|
|
ret i32 20
|
|
|
|
right_x:
|
|
ret i32 10
|
|
}
|
|
|
|
|
|
; CHECK: [[RNG4]] = !{i32 0, i32 1}
|
|
|
|
!0 = !{!3, !3, i64 0}
|
|
!1 = !{!"omnipotent char", !2}
|
|
!2 = !{!"Simple C/C++ TBAA"}
|
|
!3 = !{!"int", !1}
|
|
!4 = !{ i32 0, i32 1 }
|
|
!5 = !{ i32 8, i32 10 }
|
|
!6 = !{!6}
|
|
!7 = !{!7, !6}
|
|
!8 = !{!8, !6}
|
|
!9 = !{!7}
|
|
!10 = !{!8}
|